eGaN® FET DATASHEET
EPC2051
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1
Gallium Nitride’s exceptionally high electron mobility and low temperature coecient allows very
low R
DS(on)
, while its lateral device structure and majority carrier diode provide exceptionally low Q
G
and zero Q
RR
. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are benecial as well as those where on-state losses dominate.
EPC2051 eGaN® FETs are supplied in
passivated die form with copper pillars.
Die size: 1.3 mm x 0.85 mm
Applications
• Open Rack Server Architectures
• Lidar/Pulsed Power Applications
• Power Supplies
• Class D Audio
• LED Lighting
• Low Inductance Motor Drive
• ToF module using Vcsel laser for camera
modules, laptops and smart phones
Benets
• Ultra High Eciency
• No Reverse Recovery
• Ultra Low Q
G
• Ultra Small Footprint
EFFICIENT POWER CONVERSION
HAL
EPC2051 – Enhancement Mode Power Transistor
V
DS
, 100 V
R
DS(on)
, 25 mΩ
I
D
, 1.7 A
G
D
S
Maximum Ratings
PARAMETER VALUE UNIT
V
DS
Drain-to-Source Voltage (Continuous) 100
V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120
I
D
Continuous (T
A
= 25°C) 1.7
A
Pulsed (25°C, T
PULSE
= 300 µs) 37
V
GS
Gate-to-Source Voltage 6
V
Gate-to-Source Voltage -4
T
J
Operating Temperature -40 to 150
°C
T
STG
Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
R
θJC
Thermal Resistance, Junction-to-Case 3.8
°C/W R
θJB
Thermal Resistance, Junction-to-Board 16
R
θJA
Thermal Resistance, Junction-to-Ambient (Note 1) 92
Note 1: R
θJA
is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
# Dened by design. Not subject to production test.
Static Characteristics (T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BV
DSS
Drain-to-Source Voltage V
GS
= 0 V, I
D
= 300 µA 100 V
I
DSS
Drain-Source Leakage V
DS
= 80 V, V
GS
= 0 V 4 250 μA
I
GSS
Gate-to-Source Forward Leakage V
GS
= 5 V, T
J
= 25°C 0.001 0.2 mA
Gate-to-Source Forward Leakage
#
V
GS
= 5 V, T
J
= 125°C 0.04 2 mA
Gate-to-Source Reverse Leakage V
GS
= -4 V 4 250 μA
V
GS(TH)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= 1.5 mA 0.8 1.4 2.5 V
R
DS(on)
Drain-Source On Resistance V
GS
= 5 V, I
D
= 3 A 20 25 mΩ
V
SD
Source-Drain Forward Voltage I
S
= 0.5 A, V
GS
= 0 V 1.9 V
eGaN® FET DATASHEET
EPC2051
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 2
30
20
10
0
80
60
40
20
0
80
60
40
20
0
30
20
10
0
1.0 1.5 2.0 2.5 3.0
V
GS
= 5 V
V
GS
= 4 V
V
GS
= 3 V
V
GS
= 2 V
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
2.5 2.0 3.0 3.5 4.0 4.5 5.0 2.5 2.0 3.0 3.5 4.0 4.5 5.0
I
D
= 3 A
25
º
C
125
º
C
V
DS
= 3 V
25
º
C
125
º
C
Figure 1: Typical Output Characteristics at 25°C
Figure 3: R
DS(on)
vs. V
GS
for Various Currents Figure 4: R
DS(on)
vs. V
GS
for Various Temperatures
Figure 2: Transfer Characteristics
0 0.5
I
D
= 1.5 A
I
D
= 3.0 A
I
D
= 4.5 A
I
D
= 6.0 A
I
D
– Drain Current (A)R
DS(on)
– Drain-to-Source Resistance (mΩ)
R
DS(on)
– Drain-to-Source Resistance (mΩ) I
D
– Drain Current (A)
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
Dynamic Characteristics (T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
C
ISS
Input Capacitance
#
V
DS
= 50 V , V
GS
= 0 V
224 297
pF
C
RSS
Reverse Transfer Capacitance 1
C
OSS
Output Capacitance
#
86 129
C
OSS(ER)
Eective Output Capacitance, Energy Related (Note 2)
V
DS
= 0 to 50 V, V
GS
= 0 V
112
C
OSS(TR)
Eective Output Capacitance, Time Related (Note 3) 146
R
G
Gate Resistance 0.8 Ω
Q
G
Total Gate Charge
#
V
DS
= 50 V, V
GS
= 5 V, I
D
= 3 A 1.8 2.3
nC
Q
GS
Gate to Source Charge
V
DS
= 50 V, I
D
= 3 A
0.6
Q
GD
Gate to Drain Charge 0.3
Q
G(TH)
Gate Charge at Threshold 0.4
Q
OSS
Output Charge
#
V
GS
= 0 V, V
DS
= 50 V 7.3 11
Q
RR
Source-Drain Recovery Charge 0
# Dened by design. Not subject to production test.
Note 2: C
OSS(ER)
is a xed capacitance that gives the same stored energy as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.
Note 3: C
OSS(TR)
is a xed capacitance that gives the same charging time as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.