Datasheet

R01DS0341EJ0100 Rev.1.00 Page 1 of 65

Aug 20, 2019

RX13T Group

Renesas MCUs

Features

■ 32-bit RX CPU core

 Max. operating frequency: 32 MHz

Capable of 50 DMIPS in operation at 32 MHz

 Accumulator handles 64-bit results (for a single

instruction) from 32-bit × 32-bit operations

 Multiplication and division unit handles 32-bit × 32-bit

operations (multiplication instructions take one CPU clock

cycle)

 Built-in FPU: 32-bit single-precision floating point

(compliant to IEEE754)

 Fast interrupt

 CISC Harvard architecture with 5-stage pipeline

 Variable-length instructions, ultra-compact code

 On-chip debugging circuit

■ Low power design and architecture

 Operation from a single 2.7-V to 5.5-V supply

 Three low power consumption modes

■ On-chip code flash memory, no wait states

 128-/64-Kbyte capacities

 On-board or off-board user programming

 For instructions and operands

■ On-chip data flash memory

 4 Kbytes (1,000,000 program/erase cycles (typ.))

 BGO (Background Operation)

■ On-chip SRAM, no wait states

 12 Kbytes of SRAM

■ DMA

 DTC: Five transfer modes

■ Reset and supply management

 Seven types of reset, including the power-on reset (POR)

 Low voltage detection (LVD) with voltage settings

■ Clock functions

 Main clock oscillator frequency: 1 to 20 MHz

 External clock input frequency: Up to 20 MHz

 PLL circuit input: 4 MHz to 8 MHz

 Low-speed on-chip oscillator: 4 MHz

 High-speed on-chip oscillator: 32 MHz ±1%

 IWDT-dedicated on-chip oscillator: 15 kHz

 On-chip clock frequency accuracy measurement circuit

(CAC)

■ Independent watchdog timer

 15-kHz on-chip oscillator produces a dedicated clock

signal to drive IWDT operation.

■ Useful functions for IEC60730 compliance

 Self-diagnostic and disconnection-detection assistance

functions for the A/D converter, clock frequency accuracy

measurement circuit, independent watchdog timer, RAM

test assistance functions using the DOC, etc.

■ MPC

 Multiple locations are selectable for I/O pins of peripheral

functions

■ Up to 4 communications channels

 SCI with many useful functions (3 channels)

Asynchronous mode, clock synchronous mode, smart card

interface mode, simplified SPI, simplified I

C, and

extended serial mode.

 I

C bus interface: Transfer at up to 400 kbps (one channel)

■ Up to 8 extended-function timers

 16-bit MTU3 (six channels): 32 MHz operation, input

capture, output compare, three-phase complementary

PWM �� 1 channel-output, CPU-efficient complementary

PWM, phase counting mode (2 channels)

 16-bit compare-match timers (2 channels)

■ 12-bit A/D converter: 8 ch

 On-chip sample-and-hold circuit: 12-bit × up to 3 channels

 Sampling time can be set for each channel

 Group scan priority control mode (3 levels)

 Self-diagnostic function and analog input disconnection

detection assistance function (compliant to IEC60730)

 Input signal amplitude by the programmable gain amplifier

(3 channels)

 ADC: 3-channel simultaneous sample-and-hold circuit

(3 shunt method), double data register (1 shunt method),

amplifier (3 channels), comparator (3 channels)

■ Register write protection function can protect

values in important registers against

overwriting.

■ Up to 39 pins for general I/O ports

 5-V tolerant, open drain, input pull-up

■ Operating temperature range

 –40 to +85°C

 –40 to +105°C

■ Applications

 General industrial and consumer equipment

PLQP0048KB-B 7 × 7 mm, 0.5 mm pitch

PLQP0032GB-A 7 × 7 mm, 0.8 mm pitch

32-MHz 32-bit RX MCUs, built-in FPU, 50 DMIPS, power supply 5 V

12-bit ADC (equipped with 3-channel synchronous S/H circuits, programmable gain amplifier × 3 ch,

and comparator)

32-MHz PWM (three-phase complementary output × 1 ch), On-chip data flash memory

R01DS0341EJ0100

Rev.1.00

Aug 20, 2019

R01DS0341EJ0100 Rev.1.00 Page 2 of 65

Aug 20, 2019

RX13T Group 1. Overview

1. Overview

1.1 Outline of Specifications

Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different

packages.

Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will

differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different

Packages.

Table 1.1 Outline of Specifications (1/3)

Classification Module/Function Description

CPU CPU

 Maximum operating frequency: 32 MHz

 32-bit RX CPU

 Minimum instruction execution time: One instruction per clock cycle

 Address space: 4-Gbyte linear

 Register set

General purpose: Sixteen 32-bit registers

Control: Nine 32-bit registers

Accumulator: One 64-bit registers

 Basic instructions: 73 Variable-length instruction format

 DSP instructions: 9

 Addressing modes: 10

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit

 On-chip divider: 32-bit ÷ 32-bit → 32 bits

 Barrel shifter: 32 bits

FPU

 Single precision (32-bit) floating point

 Data types and floating-point exceptions in conformance with the IEEE754 standard

Memory ROM

 Capacity: 64 K/128 Kbytes

 32 MHz, no-wait memory access

 Programming/erasing method:

Serial programming (asynchronous serial communication), self-programming

RAM

 Capacity: 12 Kbytes

 32 MHz, no-wait memory access

E2 DataFlash

 Capacity: 4 Kbytes

 Number of erase/write cycles: 1,000,000 (typ)

MCU operating mode Single-chip mode

Clock Clock generation circuit

 Main clock oscillator, low-speed and high-speed on-chip oscillator, PLL frequency synthesizer, and

IWDT-dedicated on-chip oscillator

 Oscillation stop detection: Available

 Clock frequency accuracy measurement circuit (CAC): Available

 Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock

(FCLK)

The CPU and system sections such as other bus masters run in synchronization with the system

clock (ICLK): 32 MHz (at max.)

Peripheral modules run in synchronization with the PCLKB: 32 MHz (at max.)

The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)

The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32,

64)

Resets RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and

software reset

Voltage detection Voltage detection circuit

(LVDAb)

 When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt

is generated.

Voltage detection circuit 0 is capable of selecting the detection voltage from 3 levels

Voltage detection circuit 1 is capable of selecting the detection voltage from 9 levels

Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels

Low power

consumption

Low power consumption

functions

 Module stop function

 Three low power consumption modes

Sle

ep mode, deep sleep mode, and software standby mode

Function for lower operating

power consumption

 Operating power control modes

High-speed operating mode and middle-speed operating mode