August 2012 1

Migrating Designs from A3P250 to Lower-Logic-

Density Devices

Introduction

The purpose of this document is to assist you in migrating designs from a high-density ProASIC

3 device

(A3P250) to lower-density devices (A3P125, A3P060, and A3P030). Since one of the key factors is pin

compatibility for a given package among the devices within the family, the primary focus of this document

will be to address the pin compatibility issue.

Design Migration

ProASIC3 family devices are architecturally compatible with each other. However, customers must pay

attention to a few key areas when migrating a design. The specific issues discussed throughout this

application note are as follows:

• "Design and Device Evaluation"

• "Device and Package Compatibility" on page 2

• "Migration and Implementation Methodologies" on page 2

• "I/O Banks and Standards" on page 3

• "Power Supply Considerations" on page 4

• "Pin Migration and Compatibility" on page 5

Design and Device Evaluation

When migrating a design, the primary task should be to compare the available resources between two

devices. You need to evaluate effective gate count, RAM size, I/O banks, and the number of I/Os. In

addition, when porting designs to new ProASIC3 derivatives, timing analysis and simulations should also

be validated. Table 1 gives a summary of device resources for the A3P250 device and its smaller

migration targets.

Table 1 • Device Infor mation

A3P250 A3P125 A3P060 A3P030

System Gates 250 k 125 k 60 k 30 k

Tiles (D-flip-flops) 6,144 3,072 1,536 768

RAM (kbits) 36 36 18 –

RAM Blocks (4,608 bits) 884–

I/O Banks (+ JTAG) 4222

User I/Os per Package:

VQ100 68/13 71 71 77

QN132 87/19 84 80 81

TQ144 100 91

FG144 97/24 97 96

PQ208 151/34 133

FG256 157/38

Note: User I/O is given as X (single-ended) or X/Y (single-ended/double -ended).

Device and Package Compatibility

2 August 2012

Device and Package Compatibility

ProASIC3 devices and packaging were designed to al low considerable footprint compatibility for

smoother migration.

Common and Convertible I/Os among A3P030, A3P060, A3P125,

and A3P250

Table 2 shows the number of I/Os that are common between any two of the above four devices. In

addition, the table indicates the number of I/Os that require the necessary conversion (convertible I/Os)

using suggested design migration rules in the "Migration and Implementation Methodologies" section .

Migration and Implementation Methodologies

Table 3 on page 3 lists some possible migration combinations and the recommended implementation

rules for compatible design conversions from higher-density to lower-density devices. The "Pin Migration

and Compatibility" section on page 5 contains tables that list the required rules for different pin

combinations. If "Rule x" is mentioned for a pin combination, that combination requires the

implementation methodology given in Table 3 on page 3. Note that many combinations of high-

density/low-density pins require none of these rules; the pins have complete type compatibility. These

pins are marked in the pin tables with "None."

Table 2 • Common and Convertible I/Os

Package

A3P250

A3P125

A3P250

A3P060

A3P250

A3P030

A3P125

A3P060

A3P125

A3P030

A3P060

A3P030

Common I/Os

Convertible I/Os

Common I/Os

Convertible I/Os

Common I/Os

Convertible I/Os

Common I/Os

Convertible I/Os

Common I/Os

Convertible I/Os

Common I/Os

Convertible I/Os

VQ100 68 7 67 5 69 46 69 4 72 46 71 46

QN132 84 13 80 25 64 72 80 14 66 70 61 75

FG144 97 – 96 – N/A N/A 96 – N/A N/A N/A N/A

PQ208 134 18 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

TQ144 N/A N/A N/A N/A N/A N/A 90 19 N/A N/A N/A N/A