September 2020 United Silicon Carbide, Inc. 2
www.unitedsic.com
This report summarizes the AEC-Q101 qualification results for the 750V Discrete SiC
Cascodes in TO-247-3L and TO-247-4L plastic packages.
The environmental stress tests listed below are performed with pre-stress and post-
stress electrical tests. Reviewing the electrical results for new failures and any
significant shift in performance satisfies the qualification requirements.
Reliability Stress Test Summary
Test Name
Test Standard
# Samples
x # Lots
Failures
High Temperature
Reverse Bias
(HTRB)
MIL-STD-750-1
M1038 Method A
(1000 Hours)
T
J
=175
o
C, V=80% V
max
77x3 lots 0/231
High Temperature
Gate Bias
(HTGB)
JESD22 A-108
(1000 Hours)
T
J
=175
o
C, V=100% V
max
(+20V), bias in
one direction
77x3 lots 0/231
High Humidity, High
Temperature Reverse
Bias (H3TRB)
JESD22-A101C
(1000 Hours)
T
A
=85
o
C, 85% RH, V
GS
=0V, V
DS
=100V
77x3 lots 0/231
Temperature Cycle
(TC)
JESD22 A-104
-55
o
C to +150
o
C 2cycles/Hr
(1000 Cycles)
77x3 lots 0/231
Autoclave
(PCT)
JESD22 A-102
121°C/ RH = 100%, 96 hours, 15psig
77x3 lots 0/231
Intermittent Operating
Life (IOL)
MIL-STD-750 Method 1037
DTJ ≥125°C, 3000 cycles
(5 minutes on/ 5 minutes off)
77x3 lots 0/231
Parametric Verification Per Datasheet
100% FT x 3
lots
Physical Dimensions Per AEC-Q101 Rev D
30x1
packages
0/30
Bondline Thickness Per Assembly Spec 10x3 lots 0/30