Datasheet
R01DS0216EJ 01 2 0 Rev.1.20 Page 1 of 131
Sep 07, 2020
RX113 Group
Renesas MCUs
Features
■ 32-bit RX CPU core
• 32 MHz maximum operating frequency
Capable of 50 DMIPS when operat ing at 32 MHz
• Accumulator handles 64-bit results (for a single instr uction) from 32-
bit × 32-bit operations
• Multiplication and division u nit handles 32-bit × 32-bit operatio ns
(multiplication instructions take one CPU clock cycle)
• Fast interrupt
• CISC Harvard architecture with f ive-stage pipeline
• Variable-length instruction format, ultra-compact code
• On-chip debugging circuit
■ Low power consumption functions
• Operation from a single 1.8 to 3.6 V supply
• Three low power consumption modes
• Low power timer (LPT) that operates during the software standby
state
• Supply current
High-speed operating mode: 0.11 mA/MHz
Software standby mode: 0.44 µA
• Recovery time from software standby mode: 4.8 µs
■ On-chip flash memory for code, no wait states
• Operation at 32 MHz, read cycle of 31.25 ns
• No wait states for reading at full CPU speed
• 128 to 512 Kbyte capacities
• Programmable at 1.8 V
• For instruct i ons and operands
■ On-chip data flash memory
• 8 Kbytes
1,000,000 Erase/Write cycles (typ.)
• BGO (Background Operation)
■ On-chip SRAM, no wait states
• 32 and 64 Kbyte capaci t ie s
■ Data transfer controller (DTC)
• Four transfer modes
• Transfer can be set for each interrupt source.
■ Event link controller (ELC)
• Module operati on can be initiated by e vent signals without going
through in te rrupts.
• Link operation between modules is possible while the CPU is
sleeping.
■ Reset and power supply voltage management
• Six types incl uding Power-On Reset (POR)
• Low voltage detection (LVD) with voltage settings
■ Clock functions
• External clock input frequency: Up to 20 MHz
• Main clock oscillator frequency: 1 to 20 MHz
• Sub-clo ck oscillator frequency: 32.768 kHz
• PLL circuit input: 4 to 8 MHz
• Low-speed on-chip oscillator: 4 MHz
• High-speed on-chip oscillator: 32 MHz ±1% (–20 to 85°C)
• USB-dedicated PLL circuit: 6 and 8 MHz
• IWDT-dedicated on-chip oscillator: 15 kHz
• Generate a dedicated 32.768-kHz clock for the RTC
• On-chip clock frequency accuracy measurement circuit (CAC)
■ Realtime clock (RTC)
• 30-second, leap year, and erro r adj u st ment functio ns
• Calendar count mode or binary count mode selectable
• Capable of initiating exit from software standby mode
■ Independent watchdog timer (IWDT)
• 15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
■ On-chip functions for IEC 60730 compliance
• Clock frequency accuracy measurement circuit, IWDT, functions to
assist in RAM testing, etc.
■ Up to 12 channels for communication
• USB: USB 2.0 host/function/On-The-Go (OTG) (one channel), full-
speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and
BC (Battery Charger) supporte d
• SCI: Asynchronous mode, clock synchronous mode, smart card
interface (up to eight channels)
• IrDA interface (one channel, in cooperation with SCI5)
• I
2
C bus interface: Transfer at up to 400 kbps, capable of SMBus
operation (one channel)
• RSPI: Up to 16 Mbps (one chan nel )
• Serial sound interface (SSI) (one channel)
■ Up to 14 extended-function timers
• 16-bit MTU: Input capture/output compare, complementary PWM
output, phase counting mode
(six channels)
• 8-bit TMR (four channels)
• 16-bit CMT (four channels)
■ LCD controller/driver
• Segment signal output × common signal output:
40 × 4, 36 × 8
• On-chip voltage boost circuit, contrast adjustment, and 5-V panel
supported
• Blinking function
■ 12-bit A/D converter
• Up to 17 channels
• 1.0 µs minimum conversion speed
• Double trigger (data duplication) function for motor control
■ 12-bit D/A converter
• Two channels
■ Comparator B
• Two channels
■ Capacitive touch sensing unit (CTSU)
• Detection p i ns: 12 channels (for 100 pins only)
• High-sensitive electrostatic capacitance detec tion using
self-capac itance and mutual ca pacitance methods
• On-chip noise canceller that enables high tolerance to dist urbance
noise
• Also supports a mutu al capacitance method that allows touch
channels to be increased with low pin counts
■ Temperature sensor
■ General I/O ports
• 5-V tolerant, open drain, input pull-up
■ Multi-function pin controller (MPC)
• Multiple I/O pins can be selected for peripheral functions.
■ Unique ID
• 32-byte ID code for the MCU
■ Operating temperature range
• –40 to +85°C
• –40 to +105°C
PLQP0100KB-A 14 × 14 mm, 0.5 mm pitch
PLQP0064KB-A 10 × 10 mm, 0.5 mm pitch
PTLG0100JA-A 7 × 7 mm, 0.65 mm pitch
32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory,
USB 2.0 full-speed host/function/OTG, up to 12 comms channels, serial sound interface,
LCD controller/driver, capacitive touch sensing unit, 12-bit A/D, 12-bit D/A, RTC
R01DS0216EJ0120
Rev.1.20
Sep 07, 2020
R01DS0216EJ 01 2 0 Rev.1.20 Page 2 of 131
Sep 07, 2020
RX113 Group 1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different
packages.
Table 1.1 is for products with the greatest number of functions, so the number of peripheral modul es and channels will
differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1 Outline of Specifications (1/3)
Classification Module/Function Description
CPU CPU
• Maximum operating frequency: 32 MHz
• 32-bit RX CPU
• Minimum instruction execution time: One instruction per clock cycle
• Address space: 4-Gbyte linear
• Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
• Basic instructions: 73
• DSP instructions: 9
• Addressing modes: 10
• Data arrangement
Instructions: Lit tle endian
Data: Selectable as little endian or big endian
• On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit
• On-chip divider: 32-bit ÷ 32-bit → 32 bits
• Barrel shifter: 32 bits
Memory ROM
• Capacity: 128 K/2 56 K/384 K/512 Kbytes
• 32 MHz, no-wait memory access
• Programming/erasing method:
Serial programming (asyn ch r onous serial communication/USB communication), self-programming
RAM
• Capacity: 32 K/64 Kbytes
• 32 MHz, no-wait memory access
E2 DataFlash
• Capacity: 8 Kbytes
• Number of erase/write cycles: 1,000,000 (typ)
MCU operating mode Single-chip mode
Clock Clock generation circuit
• Main clock oscillator, sub-clock oscillator, low-speed on- chip o scillato r, high -speed on- chip o scillato r,
PLL frequency synthesizer, USB-dedicated PLL freq uency synthesizer, and IWDT-dedicated on -chip
oscillator
• Oscillation stop detection: Available
• Clock frequency accuracy measurement circuit (CAC)
• Independent settings for the system clo ck (ICLK), periphe ral module clock (PCLK), and FlashI F clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the PCLK: 32 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
• The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16 , 32,
64).
Resets RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset , and
software reset
Voltage detection Voltage detection circuit
(LVDAa)
• When the voltage on VCC f alls below the voltage detection leve l, an internal re set or int ernal interr upt
is generated.
Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Low power
consumption
Low power consumption
functions
• Module stop function
• Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Function for lower operating
power consumption
• Operating power control modes
High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt Interrupt controller (ICUb)
• Interrupt vectors: 120
• External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
• Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt,
and IWDT interrupt)
• 16 levels specifiable for the order of priority