www.latticesemi.com 1 TN1262_1.1
November 2015 Technical Note TN1262
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
The sysIO buffers in the ECP5
TM
and ECP5-5G
TM
device give the designer the ability to easily interface with other
devices using advanced system I/O standards. This technical note describes the sysIO standards available and
how to implement them using Lattice Diamond
®
design software.
sysIO Buffer Overview
The ECP5 and ECP5-5G sysIO interface contains multiple Programmable I/O Cell (PIC) blocks. The primary build-
ing block is a quad or pair of GPIO depending on the side of the I/O. The GPIO functions are available on every PIO
of all devices. The quad is built of four GPIOs (PIOA, PIOB, PIOC and PIOD) or two GPIOs (PIOA, PIOB). Two
adjacent PIOs can be joined to provide a differential I/O pair (labeled as ‘T’ and ‘C’). PIOA and PIOB comprise a
differential pair and PIOC and PIOD comprise another pair. One true LVDS driver is connected only to the A/B pair.
Each PIO includes a sysIO buffer and I/O logic (IOLOGIC). The ECP5 and ECP5-5G sysIO buffers support a vari-
ety of single-ended and differential signaling standards. The sysIO buffer also supports the DQS strobe signal that
is required for interfacing with the DDR memory. The DQS signal from the bus is used to strobe the DDR data from
the memory into input register blocks.
The top and bottom sides are grouped into eight IOs with the pitch matches to nine PLC from the core. These IOs
will support hot socket with IO standards from 3.3 V to 1.2 V and mainly used for 3.3 V domain IOs. The left and
right sides are grouped into 16 IOs that support one DQS group and pitch matches to 12PLC + EBR/DSP from the
core. The left/right side IOs will support IO standard from 3.3 V to 1.2 V with no hot socket capability. The left/right
side also have one LVDS output driver per four IOs and one differential termination resistor per two IOs. For more
information on the architecture of the sysIO buffer, refer to DS1044, ECP5 and ECP5-5G Family Data Sheet.
The IOLOGIC includes input, output and tri-state registers that implement both single data rate (SDR) and double
data rate (DDR) applications along with the necessary clock and data selection logic. Programmable delay lines
and dedicated logic within the IOLOGIC are used to provide the required shift to incoming clock and data signals
and the delay required by DQS inputs in DDR memory. The DDR implementation in the IOLOGIC and the DDR
memory interface support are discussed in more detail in TN1265, ECP5 and ECP5-5G High-Speed I/O Interface.
Supported sysIO Standards
The ECP5 and ECP5-5G sysIO buffer supports both single-ended and differential standards. Single-ended stan-
dards can be further subdivided into internally ratioed standards such as LVCMOS, LVTTL; and externally refer-
enced standards such as HSUL and SSTL. The buffers support the LVTTL, LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V standards. In LVCMOS and LVTTL modes, the buffer has individually-configurable options for drive strength,
bus maintenance (weak pull-up, weak pull-down). Differential standards supported include LVDS, BLVDS, LVPECL,
MLVDS, SLVS (Rx only), differential LVCMOS, differential SSTL and differential HSUL. For better support of video
standards, subLVDS and MIPI (Rx only) are also supported. Table 1 and Table 2 list the sysIO standards supported
in ECP5 and ECP5-5G devices.
ECP5 and ECP5-5G
sysIO Usage Guide
2
ECP5 and ECP5-5G sysIO Usage Guide
Table 1. Single-Ended I/O Standards
Table 2. Differential I/O Standards
sysIO Banking Scheme
ECP5 and ECP5-5G devices have general-purpose programmable sysIO banks and a configuration bank. Each of
the general-purpose sysIO banks has a V
CCIO
supply voltage and one reference voltage, V
REF1
. Every device has
two banks on the left, right and top side.
The bottom side implements SERDES channels and only the biggest device 85K has one sysIO bank.
Every ECP5 and ECP5-5G device has a TAP controller interface bank in the lower left corner of the device. This
Bank 8 has four signal pins (TCK, TMS, TDI and TDO) and is powered by V
CCIO8
, located on the lower left side of
the device, has shared I/O for configuration.
Standard V
REF
V
CCIO
Input Output Bi-Directional
LVTTL33 —
3.3
2
Ye s Ye s Ye s
LVCMOS33 —
3.3
2
Ye s Ye s Ye s
LVCMOS25 —
2.5
2
Ye s Ye s Ye s
LVCMOS18 — 1.8 Yes Yes Yes
LVCMOS15 — 1.5 Yes Yes Yes
LVCMOS12 —
1.2
2
Ye s Ye s Ye s
SSTL18 Class I, II 0.9 —
Ye s
1
Ye s
Ye s
1
SSTL15 Class I, II 0.75 —
Ye s
1
Ye s
Ye s
1
SSTL135 Class I, II 0.675 —
Ye s
1
Ye s
Ye s
1
HSUL12 0.6 —
Ye s
1
Ye s
Ye s
1
1. Left and right side I/O only.
2. Required for output only.
Standard V
REF
Input Output Bi-Directional
SSTL18D I, II —
SSTL135D I, II —
SSTL15D I, II —
HSUL12D —
LVTTL33D —
LVCMOS33D —
LVCMOS25D —
LVCMOS18D —
LVDS — Yes A/B pair Yes
LVDS25E — No Yes No
BLVDS25 — Yes No No
BLVDS25E — No Yes Yes
MLVDS25 — Yes No No
MLVDS25E — No Yes Yes
LVPECL33 — Yes No No
LVPECL33E — No Yes No
SLVS — Yes No No
SUBLVDS — Yes No No
MIPI D-PHY HS Mode — C/D Pair No No