www.latticesemi.com 1 TN1267_1.1
November 2015 Technical Note TN1267
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
This technical note discusses how to access the features of the ECP5™ and ECP5-5G™ sysDSP™ (Digital Signal
Processing) slice described in DS1044, ECP5 and ECP5-5G Family Data Sheet. ECP5 and ECP5-5G devices are
optimized to support high-performance DSP applications, such as wireless base station channel cards, Remote
Radio Head (RRH) systems, video and imaging applications, and Fast Fourier Transform (FFT) functions.
sysDSP Overview
Figure 1 shows the ECP5 and ECP5-5G device DSP Block Diagram at a higher level. As shown each DSP slice
has two 18-bit pre-adders, pre-adder registers, two 18-bit multipliers, input registers, pipeline registers, 54-bit ALU,
output registers.
Figure 1. ECP5 and ECP5-5G DSP Block Diagram Overview
sysDSP slices are located in rows throughout the device. Figure 2 shows the simplified block diagram of the sys-
DSP slices. The programmable resources in a slice include the pre-adders, multipliers, ALU, multiplexers, pipeline
registers, shift register chain and cascade chain. If the shift out register A is selected, the cascade match register
(Casc) is available. The pre-adders and the multipliers can be configured as 9 bits or 18 bits wide and the ALU can
+/-
P2
2C
2A
2A
28
29
24
27
21
26
25
2M22M1
X
X
Double edge register, works at both rising and falling edges
19
+/-
23
2A
+/-
2OP
2C1
2C2
MUIC1
[26:0]
MUIC1
[53:27]
MUIA3 MUIB3MUIA2 MUIB2
OPCODE
_PA[3:2]
2
25
25
'0'
MUX_FB1
22 '0'
2
2C2
'0''0'
2C1
MUIA2
MUIA3
MUX_PA3
MUX_PA2
MUIB2
MUIB3
[2] [3]
2C1 2C2
OPA2
OPA3
MUIA2
MUIA3
+/-
P1
1C
1A
2A
18
14
17
11
16
15
1M21M1
X
X
Traditional DFF, works at rising edge only
+/-
13
12
+/-
1OP
1C1
1C2
MUIC1
[26:0]
MUIC1
[53:27]
MUIA1 MUIB2MUIA0 MUIB0
OPCODE
_PA[1:0]
2
25
15
'0'
MUX_FB0
12 '0'
2
1C2
'0'
'0'
1C1
MUIA0
MUIA1
MUX_PA1
MUX_PA0
MUIB0
MUIB1
[0] [1]
1C1 1C2
OPA0
OPA1
MUIA0 MUIA1
1C2 1A
2A
1A
2A
2C2 1A
2A
1A
2A
LFE5 DSP Slice
LFE5 DSP Slice
LFE5
DSP Slice
LFE5
DSP Slice
SROB
SRIA
SOURCE A
MODE
SYMMETRY
MODE
PO
SOURCE A
MODE
PA PB
SRIB
SROA
ECP5 and ECP5-5G sysDSP
Usage Guide
2
ECP5 and ECP5-5G sysDSP Usage Guide
be configured as 24 bits or 54 bits wide. Multipliers and accumulators can be configured independently and can be
used as stand-alone primitives. However, pre-adders must only be used in conjunction with the associated multi-
plier block. Advanced features of the sysDSP slice are described later in this document.
Figure 2. ECP5 and ECP5-5G DSP Slice Detailed View
Figure 2 shows the individual ECP5 and ECP5-5G sysDSP slice in greater detail. It shows dual pre-adders with the
core ECP5 and ECP5-5G DSP logic. The built-in pre-adders, multipliers and ALU minimize the amount of external
logic required to implement some of the key DSP functions, resulting in efficient resource usage, reduced power
consumption, improved performance, and data throughput for DSP applications. The ECP5 and ECP5-5G sysDSP
slice can be configured several ways to suit users’ end applications.
The IR shown in a blue outline is an 18-bit register. The ORs and FR share a 72-bit register. If simple multiplier
mode is implemented, the register is used as multiplier output. If ALU is implemented, it is used as ALU output.
MUIA0 MUIB0 OPCODE_PA MUIA1 MUIB1
INT_A INT_B
INT_B
INT_A
IR
IR IR
IR
IR
IR
IR
IR IR
IR
DSP SLICE
DSP
Core
Logic
FLAGSR
ALU
CMUX
CIN
C_ALU
A ALU
B ALU
Shift 18L
MULTA MULTB
0
0
SRIB
SRIA
C
OPA0
DYNOP OPA1
SROA
SROB
SRIBK_PA
IR
MUOP1
IR
DSP
PreAdder
Logic
MUOP0
R= A ± B ± C
R = Logic (B, C)
BMUXAMUX
PRPR
OR
COUT
OROR FR
=
=
PR
=
+/-
+/-