www.latticesemi.com 1 TN1265_1.1
November 2015 Technical Note TN1265
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
ECP5
TM
and ECP5-5G
TM
devices support high-speed I/O interfaces, including Double Data Rate (DDR) and Single
Data Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture data
on one edge of a clock while DDR interfaces capture data on both the rising and falling edges of the clock, thus
doubling the performance. ECP5 and ECP5-5G device I/Os also have dedicated circuitry that is used along with
the DDR I/O to support DDR2, DDR3, DDR3L, LPDDR2 and LPDDR3 SDRAM memory interfaces.
This document discusses how to utilize the capabilities of the ECP5 and ECP5-5G devices to implement high-
speed generic DDR interface and the DDR memory interfaces. Refer to the Implementing DDR Memory Interfaces
section of this document for more information.
External Interface Description
This technical note uses two types of external interface definitions, centered and aligned. A centered external inter-
face means that, at the device pins, the clock is centered in the data opening. An aligned external interface means
that, at the device pins, the clock and data transition are aligned. This is also sometimes called edge-on-edge.
Figure 1 shows the external interface waveform for SDR and DDR.
Figure 1. External Interface Definitions
The interfaces described are referenced as centered or aligned interfaces. An aligned interface will need to adjust
the clock location to satisfy the capture flip-flop setup and hold times. A centered interface will need to balance the
clock and data delay to the first flip-flop to maintain the setup and hold already provided.
SDR Aligned
DDR Aligned
SDR Centered
DDR Centered
ECP5 and ECP5-5G
High-Speed I/O Interface
2
ECP5 and ECP5-5G High-Speed I/O Interface
High-Speed I/O Interface Building Blocks
ECP5 and ECP5-5G devices contain dedicated functions for building high-speed interfaces. This section describes
when and how to use these functions. A complete description of the library elements, including descriptions and
attributes, is provided at the end of this document.
Figure 2 shows a high-level diagram of the clocking resources available in the ECP5 and ECP5-5G devices for
building high-speed I/O interfaces.
Figure 2. ECP5 and ECP5-5G Device Clocking Diagram
A complete description of the ECP5 and ECP5-5G device family clocking resources and clock routing restrictions
are available in TN1263, ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide.
Below is a brief description of each of the major elements used for building various high-speed interfaces. The
DDR Software Primitives and Attributes section of this document describes the library elements for these compo-
nents.
Edge Clocks
Edge clocks (ECLK) are high-speed, low-skew I/O dedicated clocks. They are arranged in groups of two per I/O
bank on the left and right sides of the device. Each of these edge clocks can be used to implement a high speed
interface. There is an Edge Clock Bridge (ECLKBRIDGECS) that will allow users to build large interfaces by bridg-
ing the edge clocks from one bank to the other on the same side or from one side to the other side.
Primary Clocks
Primary clocks (PCLK) refer to the system clock of the design. The SCLK ports of the DDR primitives are con-
nected to the system clock of the design.
DQS Lane
A DQS Lane uses the embedded circuit for memory interfaces. Each DQS Lane provides a clock pair (DQSP and
DQSN) for the DQS strobe and up to 12 to 16 ports for DQ data and DM data mask signals. The number of DQS
Lanes on the device is different for each device size. ECP5 and ECP5-5G devices support DQS lanes on the left
and right sides of the device.
Center MUX
Mid
MUX
Mid
MUX
Quadrant TL
Quadrant BL
Quadrant TR
Quadrant BR
GPLL
CLK
DIV
PIOPIOPIOPIO
GPLL
CLK
DIV
PIO PIO PIO PIO
Edge Clocks
Mid
MUX
Edge Clocks
GPLL
CLK
DIV
PIO PIO
PIO
PIO
GPLL
CLK
DIV
Edge Clocks
Mid
MUX
Edge Clocks
SERDES DCU1
Bank0 Bank1
Bank2 Bank3
Bank6 Bank7
PCSCLKDIV
PCSCLKDIV
SERDES DCU0
Fabric
Entry
Fabric
Entry
Fabric
Entry
Fabric
Entry
14
12
16
Primary Sources
Primary Sources
Primary Sources
Primary Sources
Primary
Clocks
Primary
Clocks
Primary
Clocks
Primary
Clocks
16
16
16
16
Bank8
14 DCC
14
14
14 DCC
14
12 DCC
16 DCC
Bank4