www.latticesemi.com 25-1 an6078_01.1

April 2011 Application Note AN6078

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

This application note discusses the states of the Power Manager II ispPAC

-POWR607 device’s output pins –

Open drain logic outputs (IN_OUT3 to IN_OUT7) and HVOUT – during power-up, reset, and JTAG programming,

as well as the states of these pins on a device that has not yet been programmed by the user. Suggested methods

for interfacing to the enable pin of DC/DC converters and for performing in-system programming are also covered

in this application note.

Power-on Reset State

The ispPAC-POWR607 contains on-chip power-on reset circuitry to ensure that all parts of the device start up reli-

ably, regardless of VCC ramp rate. As shown in Figure 25-1, the device enters the power-on reset state when VCC

is typically at 0.8V. When VCC is greater than 2.5V, the device will exit the power-on reset state after T

RST

delay.

During power-on reset state, the output pins will go to the states shown in Table 25-1. After the device exits the

power-on reset state, any brownouts that cause the VCC supply to dip below 2.5V will cause the device to re-enter

the power-on reset state. An internally generated power-on-reset (POR) signal becomes active during the power-

on reset state. The POR signal is used to asynchronously reset or preset the macrocells within the PLD. The

designer can specify whether an output is reset or preset by using the PINS window of LogiBuilder in PAC-

Designer. By default all the state machine macrocells are reset so the device will start-up in Step 0.

Table 25-1. Output States During Power-On Reset

Figure 25-1. Internal Power-On Reset

Output Type Power-on Reset State

IN_OUT3 to IN_OUT7 High Impedance

HVOUT, Charge Pump Mode (as-shipped) High Impedance

HVOUT, Open Drain Logic Output Mode High Impedance

VCC

POR (Internal)

VMONs Ready (Internal)

START

PLDCLK (Internal)

Reset

State

Analog

Calibration

RST

BRO

Start Up State

POR

Powering Up and Programming the

ispPAC-POWR607

Powering Up and Programming

Lattice Semiconductor the ispPAC-POWR607

25-2

Start-up State

The ispPAC-POWR607 exits the power-on reset state and enters the start-up state as the internal POR signal

becomes active. The start-up state initializes and enables additional circuits before releasing the PLD-clock. During

the start-up state the VMON comparator outputs are Low, the PLD-clock is inactive, and the analog circuits are cal-

ibrated. The end of the start-up state is signified with the first rising edge of the PLD-Clock, which is applied to all

the programmable registers within the device. The analog circuit calibration is typically completed 4 µs before the

end of the start-up state.

Figures 25-2-25-5 illustrate the power-on reset behavior associated with logic outputs IN_OUT3 to IN_OUT7 and

HVOUT pins that have been programmed to operate as open drain logic outputs. 2k Ohm pullup resistors to the

VCCD pin were used on the logic output pins in all of the plots.

Figure 25-2. Startup with Slow Supply; Output Resets Low

Figure 25-3. Startup with Slow Supply; Output Resets High

Figures 25-2 and 25-3 show an open drain logic output pin that has been programmed to behave as a registered

output. The difference between these two plots is that in Figure 25-2, the output has been programmed to reset to

a low level, whereas in Figure 25-3, it has been programmed to reset high. The power supply goes from zero to

3.3V in 20 milliseconds. The waveforms in Figures 25-2 and 25-3 are typical of VCC supplies that take more than a

millisecond to reach 3.3V.

10 ms/div