www.latticesemi.com 7-1 an6073_01.1

April 2011 Application Note AN6073

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

This application note discusses the states of the Power Manager II ispPAC

-POWR1220AT8 device’s output pins

— Open drain logic outputs (OUT5-OUT20), HVOUT, and Trim DAC — during power-up, reset, and JTAG program-

ming, as well as the states of these pins on a device that has not yet been programmed by the user. An under-

standing of this aspect of the device’s operation is the key to designing systems that sequence supplies on in a

dependable fashion. Suggested methods for interfacing to the enable pin of DC/DC converters and for performing

in-system programming are also covered in this application note.

Power-on Reset

The ispPAC-POWR1220AT8 contains on-chip power-on reset circuitry to ensure that all parts of the device start up

reliably, regardless of the speed at which the VCC supply to the device reaches 3.3V. The device enters power-on

reset when VCC is approximately 0.8V. VCC must reach a voltage greater than 2.5V for the device to exit power-on

reset. During power-on reset, the output pins will go to the states shown in Table 7-1. After the device exits power-

on reset, any brownouts that cause the VCC supply to dip below 2.5V will cause another power-on reset event to

occur.

Table 7-1. Output States During Power-On Reset

The ispPAC-POWR1220AT8 has a bi-directional reset pin (RESETb) whose main purpose is to synchronize the

startup of multiple Power Manager devices. This pin can also be used to indicate when the device is in power-on

reset. Figure 7-1 shows an equivalent circuit for this pin; it is an open-drain output with a built-in pullup resistance to

VCCD. External pullup resistors to VCCD may be used but are not necessary. No capacitors should be connected

to this pin because they will degrade the slew rate of the reset waveform. Unlike conventional active-low reset pins,

RESETb should never be connected directly to the VCC supply.

Figures 7-2-7-5 illustrate the power-on reset behavior associated with logic outputs OUT5-20 and HVOUT pins that

have been programmed to operate as open drain logic outputs. 2k Ohm pullup resistors to the VCCD pin were

used on both the RESETb and logic output pins in all of the plots.

Figure 7-1. RESETb Pin Equivalent Circuit

Output Type Power-on Reset State

OUT5-OUT20 High Impedance

HVOUT, Charge Pump Mode (as-shipped) Pull-down

HVOUT, Open Drain Logic Output Mode High Impedance

Trim DAC High Impedance

From POR Circuitry

Internal Reset

VCCD

ispPAC-POWR1220AT8

RESETb

To additional

ispPAC-POWR1220AT8

devices

Powering Up and Programming the

ispPAC-POWR1220AT8

Powering Up and Programming

Lattice Semiconductor the ispPAC-POWR1220AT8

7-2

Figures 7-2 and 7-3 show an open drain logic output pin that has been programmed to behave as a registered out-

put. The difference between these two plots is that in Figure 7-2, the output has been programmed to reset to a low

level, whereas in Figure 7-3, it has been programmed to reset high. The power supply goes from zero to 3.3V in 20

milliseconds. The waveforms in Figures 7-2 and 7-3 are typical of VCC supplies that take more than a millisecond

to reach 3.3V.

Figure 7-2. Startup with Slow Supply; Output Resets Low

Figure 7-3. Startup with Slow Supply; Output Resets High

The behavior in both cases is identical until the time that VCC reaches 2.5V. RESETb pulls down starting at a VCC

voltage of 0.8V; the RESETb output thus follows VCC up until this point. The open drain logic output retains its high

impedance state until VCC reaches 2.5V; the voltage observed at the open drain logic output thus follows VCC to

2.5V. When VCC reaches 2.5V, power-on reset ends. From that point on, RESETb goes to a high level, and the

logic outputs assume their programmed macrocell reset levels.

Figures 7-4 and 7-5 show the waveforms observed when the same device and setup that were examined in Fig-

ures 7-2 and 7-3 are powered from a supply that goes from 0 to 3.3V in 100 microseconds. Despite the faster

power-up rate, RESETb still indicates that power-on reset starts when VCC reaches 0.8V. At this faster power-up

rate, however, the time at which power-on reset ends is dominated by the time that it takes for the logic circuitry

inside the ispPAC-POWR1220AT8 device to initialize, rather than occurring when VCC crosses 2.5V. Regardless of