Voltage Monitoring for Fault Logging
with ispPAC-POWR1220AT8
April 2010 Reference Design RD1072
www.latticesemi.com 1 rd1072_01.0
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
For systems using microprocessors or computers there are usually numerous power supplies. If a power supply
fails the power manager circuits may, as a minimum, force a shutdown. For maintenance and troubleshooting it is
very desirable to know which power supply failed and the type of failure condition (over-voltage or under-voltage).
This reference design presents a solution that records the supply fault condition in non-volatile memory so the
fault(s) can read back at a later time. This solution is fast, reliable, and cost effective because it is based on a
Power Manager II, MachXO™ or LatticeXP2™ and non-volatile SPI Flash memory.
Theory of Operation
This fault logger reference design uses a Lattice Power Manager II device to monitor the voltage levels in the sys-
tem. The Power Manager II device is designed to monitor and control different power supplies within a system and
has an on-board analog-to-digital converter. The user can set high and low voltage alarm points within the device
and these can then be used to initiate different control actions of the user’s choosing. For this design a voltage
alarm will cause a fault status output to be driven high and the status of all the voltage monitor channels to be out-
put on four data status lines. This design uses the ispPAC
®
-POWR1220AT8 Power Manager II device but could
also be adapted to the ispPAC-POWR1014A device.
The fault status output and the four data status lines are connected to a MachXO or LatticeXP2 device which then
captures the fault data, formats it, and writes the formatted data to a SPI Flash memory for later retrieval.
The sequence of events can be summarized as follows:
1. The ispPAC-POWR1220AT8 detects a fault on one or more of the VMON inputs and dumps the status of all
the VMON inputs to the MachXO or LatticeXP2 device.
2. The dump of VMON status is implemented using supervisory logic equations and happens automatically
using outputs and clock pins of the Power Manager II.
3. The MachXO or LatticeXP2 implements a receiver state machine to capture the VMON status.
4. The MachXO or LatticeXP2 adds a time stamp to the VMON status information, sends the commands and
writes the data to a SPI Flash memory device.
A block diagram of the Fault Logging Reference Design is shown in Figure 1.
Voltage Monitoring for Fault Logging
Lattice Semiconductor with ispPAC-POWR1220AT8
2
Figure 1. Fault Logging Design Block Diagram
Design Details
Figure 3 shows the details of the VMON status dump from the Power Manager II to the MachXO or LatticeXP2
device and the transfer of data from the MachXO or LatticeXP2 device to the SPI Flash memory. The VMON status
dump is generated within the Power Manager II device using an internal 250 KHz clock (fixed) which also drives the
PCLK signal. The PCLK signal is used to drive the VMON Status Capture state machine inside the MachXO or
LatticeXP2 device.
As shown in Figure 1, the fault logging process is divided between two devices; the Power Manager II detects and
dumps the faults to the CPLD that captures the faults. The CPLD then writes them to a standard non-volatile SPI
memory. The CPLD also provides arbitration logic, a timer, and a MUX interface to the SPI memory for micropro-
cessor support. The details of the CPLD design are presented in RD1092 Fault Logging Twelve Power Supplies
using the MachXO. This document discusses the details of the Power Manager ispPAC-POWR1220AT8 design file
RD1072_Fault_Logging.PAC, which is targeted for demonstration on the Power Manager Hercules Evaluation
Board.
The heart of this design is contained in the supervisory logic equations in the LogiBuilder window of PAC-
Designer
®
(see Listing 2). One set of equations is used to implement a three-bit binary up-counter and the second
set of equations is used to dump all the VMON status values to the CPLD. When the counter is active the four-bit
bus of output pins is updated with the VMON status values on the rising edge of the PLD clock (250 kHz). The ris-
ing edge of the fifth output (OUT20_PM_FLT4) is used to trigger the CPLD to capture the VMON status.
OUT16 - PM_FLT0
OUT17 - PM_FLT1
OUT18 - PM_FLT2
OUT19 - PM_FLT3
250kHz - PCLK
Fault Detection and Dump
ispPAC-POWR1220AT8
Fault Capture and Logger
MachXO or LatticeXP2-5E
VMON
Status
Dump
State
Machine
VMON
1-12
A & B
VMON
Status
Capture
State
Machine
SPI Memory
SS
SCLK
MOSI
MISO
M
U
X
SPI
Write
Status
State
Machine
Sequencer &
Supervisory Logic
Arbitration Logic
and Handshaking
Busy Ready
Mem
Clear
Timer
SS
SCLK
MOSI
MISO
8MHz - MCLK
SS
SCLK
MOSI
MISO
SPI
Full
OUT20 - PM_FLT4
Microprocessor Interface
Reset