1 A Low-Cost, High Performance Data Acquisition & Control Card Using
LatticeECP/EC FPGAs and Lattice ispPAC Power Manager
A Lattice Semiconductor White Paper
A Low-Cost, High Performance
Data Acquisition & Control Card Using
LatticeECP/EC FPGAs and
Lattice ispPAC Power Manager
A Lattice Semiconductor White Paper
April 2005
Lattice Semiconductor
5555 Northeast Moore Ct.
Hillsboro, Oregon 97124 USA
Telephone: (503) 268-8000
www.latticesemi.com
2 A Low-Cost, High Performance Data Acquisition & Control Card Using
LatticeECP/EC FPGAs and Lattice ispPAC Power Manager
A Lattice Semiconductor White Paper
Introduction
Off-the-shelf data acquisition and control cards with an on-board DSP CPU often
perform at only a fraction of their benchmark-based expectations. Increasing the
number of channels, or increasing the sampling rate, begins to show signs of
DSP CPU overload well before reaching full channel capacity.
Present day market pressures are forcing data acquisition and control card
providers to increase the number of channels on a data acquisition card,
increase the sampling rate and, at the same time, reduce cost. Further, the
actual function of the card is determined either during manufacturing or
configured in-system. Sometimes the same card will be expected to perform
different functions at different slots on the same system.
The use of DSP CPU on board, while providing the flexibility of hardware reuse
across a wide range of applications, also becomes a bottleneck for board level
performance.
DSP CPU Efficiency Decreases with
Increased Channel Loading
As the number of channels increases, the load on the DSP engine also
increases. This is due to the serial processing nature of current DSP CPUs,
which are fetch/execute engines. In most applications, most of the DSP CPU's
bandwidth is consumed in front-end pre-processing tasks (offset shifting, gain
adjustment, preliminary filtering, etc.). Developing this code is also difficult and
time consuming because, for efficiency reasons, it is usually coded in assembly
language. Even though the transfer of samples from each channel to different
memory locations is handled by DMA, CPU performance suffers due to the
reduced availability of memory bandwidth. The faster the sample rate, the less
time is available for the processor to perform the actual DSP functions such as
signal analysis, video processing, compression, etc.