www.latticesemi.com 23-1 an6075_01.1

April 2011 Application Note AN6075

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

This application note discusses the states of the Power Manager II ispPAC

-POWR1014/A device’s output pins —

Open drain logic outputs (OUT3-OUT14) and HVOUT — during power-up, reset, and JTAG programming, as well

as the states of these pins on a device that has not yet been programmed by the user. An understanding of this

aspect of the device’s operation is the key to designing systems that sequence supplies on in a dependable fash-

ion. Suggested methods for interfacing to the enable pin of DC/DC converters and for performing in-system pro-

gramming are also covered in this application note.

Power-on Reset

The ispPAC-POWR1014/A contains on-chip power-on reset circuitry to ensure that all parts of the device start up

reliably, regardless of the VCC ramp rate. The device enters power-on reset when VCC is approximately 0.8V. VCC

must reach a voltage greater than 2.5V for the device to exit power-on reset. During power-on reset, the output pins

will go to the states shown in Table 23-1. After the device exits power-on reset, any brownouts that cause the VCC

supply to dip below 2.5V will cause another power-on reset event to occur.

Table 23-1. Output States During Power-On Reset

The ispPAC-POWR1014/A has a bi-directional reset pin (RESETb) whose only purpose is to synchronize the

startup of multiple Power Manager II devices. Figure 23-1 shows an equivalent circuit for this pin; it is an open-drain

output with a built-in pullup resistance to VCCD. If this pin is not being used to cascade multiple Power Manager II

devices, it should be left unconnected.

Figures 23-2-23-5 illustrate the power-on reset behavior associated with logic outputs OUT3-14 and HVOUT pins

that have been programmed to operate as open drain logic outputs. 2k Ohm pullup resistors to the VCCD pin were

used on the logic output pins in all of the plots.

Figure 23-1. RESETb Pin Equivalent Circuit

Figures 23-2 and 23-3 show an open drain logic output pin that has been programmed to behave as a registered

output. The difference between these two plots is that in Figure 23-2, the output has been programmed to reset to

Output Type Power-on Reset State

OUT3-OUT14 High Impedance

HVOUT, Charge Pump Mode (as-shipped) Pull-down

HVOUT, Open Drain Logic Output Mode High Impedance

From POR Circuitry

Internal Reset

VCCD

ispPAC-POWR1014/A

RESETb

Should be used ONLY

to synchronize additional

ispPAC-POWR1014/A

devices

Powering Up and Programming the

ispPAC-POWR1014/A

Powering Up and Programming

Lattice Semiconductor the ispPAC-POWR1014/A

23-2

a low level, whereas in Figure 23-3, it has been programmed to reset high. The power supply goes from zero to

3.3V in 20 milliseconds. The waveforms in Figures 23-2 and 23-3 are typical of VCC supplies that take more than a

millisecond to reach 3.3V.

Figure 23-2. Startup with Slow Supply; Output Resets Low

Figure 23-3. Startup with Slow Supply; Output Resets High

The behavior in both cases is identical until the time that VCC reaches 2.5V. RESETb pulls down starting at a VCC

voltage of 0.8V; the RESETb output thus follows VCC up until this point. The open drain logic output retains its high

impedance state until VCC reaches 2.5V; the voltage observed at the open drain logic output thus follows VCC to

2.5V. When VCC reaches 2.5V, power-on reset ends. From that point on, RESETb goes to a high level, and the

logic outputs assume their programmed macrocell reset levels.

Figures 23-4 and 23-5 show the waveforms observed when the same device and setup that were examined in Fig-

ures 23-2 and 23-3 are powered from a supply that goes from 0 to 3.3V in 100 microseconds. Despite the faster

power-up rate, RESETb still indicates that power-on reset starts when VCC reaches 0.8V. At this faster power-up

rate, however, the time at which power-on reset ends is dominated by the time that it takes for the logic circuitry

inside the ispPAC-POWR1014/A device to initialize, rather than occurring when VCC crosses 2.5V. Regardless of

the VCC supply ramp rate, the low-to-high transition of RESETb indicates that the logic circuitry is ready to operate,

and the outputs can be observed going to their programmed states.