www.latticesemi.com
1
tn1131_02.0
April 2007 Technical Note TN1131
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
Clock Boosting, supported in Lattice Semiconductor’s FPGA device families, is the introduction of clock skew on a
target flop to increase the setup margin. The implementation of this clock skew is accomplished in two different
approaches. One approach is to use programmable delay taps built into the architecture in the LatticeSC™ and
LatticeSCM™ device families. The second approach inserts delays determined algorithmically into the clock tree to
provide additional clock skew in the LatticeEC™, LatticeECP™, LatticeXP™ and MachXO™ device families. The
two approaches are described below.
LatticeSC/M Device Families
Clock Boosting is the introduction of clock skew on a target flop to increase the setup margin. To implement this
clock skew, every programmable flip-flop in the device features programmable delay elements located in front of
the clock inputs. The automated Clock Boosting tool will attempt to meet setup constraints by introducing delays to
as many target registers as needed to meet timing. In effect, it borrows from the slow path setup time. The following
bullets summarize how Clock Boosting is accomplished in the LatticeSC/M device families.
• A 4-tap delay cell structure in front of the clock port of every flip-flop in the device (including I/O flip-flops).
• Ability to borrow clock cycle time from one easily-met path and give this time to a difficult-to-meet path.
Clock Boosting is typically most useful in designs that are only missing timing on a few paths for one or two prefer-
ences. If the design is missing timing by more than a few nanoseconds on any given path, Clock Boosting will not
be able to schedule skew in a way that will eliminate enough timing errors to make the critical preference.
Figure 1. LatticeSC/M Clock Boosting Example
The example illustrated in Figure 1 shows two register-to-register transfers that both need to meet the 10 ns period
constraint. By using delay cell DEL2 to delay the clock input on flip-flop FF_2, the first register transfer will make its
period constraint with a new minimum period of ~9.7 ns and the second register transfer will make its period con-
straint by ~8.3 ns.
The D1, D2, and D3 delays shown in Figure 1 are variable depending on the speed grade and Lattice FPGA device
family.
DEL1 ~= 0.7 ns
DEL2 ~= 1.3 ns
DEL3 ~= 2.0 ns
DEL1
DEL2
DEL3
FF_1
Clock
Target Performance: 10 ns period (100 MHz)
FF_2 FF_3
7 ns11 ns
Combinational
Logic
Clock Boosting in
Lattice FPGAs
2
Lattice Semiconductor Clock Boosting in Lattice FPGAs
To Run Clock Boosting in the Project Navigator:
1. In the Project Navigator Sources window, select the target device (LatticeSC/M).
2. In the Processes window, right-click
Clock Boosting
under the
Place & Route Design
process, and then
select
Properties
to open the Properties dialog box.
3. Select the
Clock Boosting Output Filename
property from the property list and type the name of the out-
put file name in the edit region (<file_name>.ncd).
4. To select the Clock Boosting Mode click on
Clock Boosting Mode
, then click on the down arrow, to the left
of the Close box, then select from
Basic Clock Boost, “Maximize Frequency
or
Hold-time Correction
only
.
5. Click
Close
to close the dialog box.
As shown in Figure 2, the original .ncd and .prf files as well as the output .ncd file are typed into the corresponding
entries. Checking
Maximize Frequency
will push the tool to improve the frequency beyond the input preference
requirement. This is generally only useful for benchmarking.
Figure 2. Clock Boosting Properties Window for LatticeSC/M
Other important considerations on the practicality of using clock boosting:
• Some circuits show big improvements, while others have no gain. Clock Boosting results are design-dependent.
• Clock Boosting uses maximum and minimum delay values.
• Automatic clock boosting identifies skew and tries to fix hold time issues, it will not cause more hold time viola-
tions. If the designer would like to double check the results, run Trace twice, once with regular, maximum delay
analysis, and again with minimum delays. The designer should then read over both resultant .twr timing reports
to make sure there are no timing errors. The minimum delay analysis is done by checking the Check Hold Times
checkbox in the Trace Options GUI window.
Based on recent LatticeSC/M benchmark data, Clock Boosting achieves 11% f
MAX
gain on average. The test
results range from 0% to 28%.
LatticeECP/EC, LatticeXP and MachXO Device Families
Clock Boosting, supported in the LatticeECP/EC, LatticeXP and MachXO device families, is the introduction of
clock skew on a target flop to increase the setup margin. To implement this clock skew, every synchronized flip-flop
in the device uses a placed and routed NCD file. This process first finds the optimal clock skew for each flip-flop,
then inserts unused general routing resources into the clock tree to provide additional clock skew. The Clock Boost-
ing algorithm will attempt to meet setup constraints by introducing delays to as many target registers as needed to