8-/6-/4-Channel DAS with 16-Bit, Bipolar
Input, Simultaneous Sampling ADC
Data Sheet
AD7606/AD7606-6/AD7606-4
Rev. F Document Feedback
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FEATURES
8/6/4 simultaneously sampled inputs
True bipolar analog input ranges: ±10 V, ±5 V
Pin to pin compatible with the state-of-the-art AD7606B
Single 5 V analog supply and 2.3 V to 5 V V
DRIVE
Fully integrated data acquisition solution
Analog input clamp protection
Input buffer with 1 MΩ analog input impedance
Second-order antialiasing analog filter
On-chip accurate reference and reference buffer
16-bit ADC with 200 kSPS on all channels
Oversampling capability with digital filter
Flexible parallel/serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Performance
7 kV ESD rating on analog input channels
95.5 dB SNR, −107 dB THD
±0.5 LSB INL, ±0.5 LSB DNL
Low power: 100 mW
Standby mode: 25 mW
Temperature range: −40°C to +85°C
64-lead LQFP package
APPLICATIONS
Power-line monitoring and protection systems
Multiphase motor control
Instrumentation and control systems
Multiaxis positioning systems
Data acquisition systems (DAS)
Table 1. High Resolution, Bipolar Input, Simultaneous
Sampling DAS Solutions
Resolution
Single-
Ended
Inputs
True
Differential
Inputs
Number of
Channels
18 Bits AD7608 AD7609 8
16 Bits AD7606B
1
8
AD7606 8
AD7606-EP 8
AD7606-6 6
AD7606-4 4
AD7605-4 4
14 Bits AD7607 8
1
This state-of-the-art device is recommended for newer designs as an alternative
to the AD7606.
FUNCTIONAL BLOCK DIAGRAM
V1
V1GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDE R LPF
T/H
V2
V2GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDE R LPF
T/H
V3
V3GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDE R LPF
T/H
V4
V4GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDE R LPF
T/H
V5
V5GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDE R LPF
T/H
V6
V6GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDE R LPF
T/H
V7
V7GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDE R LPF
T/H
V8
V8GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDE R LPF
T/H
8:1
MUX
AGND
BUSY
FRSTDATA
CONVS T A
CONVS T B
RESET RANGE
CONTROL
INPUTS
CLK O SC
REFIN/REFOUT
REF SELECT
AGND
OS 2
OS 1
OS 0
D
OUT
A
D
OUT
B
RD/SCLK
CS
PAR/SER/ BYTE SEL
V
DRIVE
16-BIT
SAR
DIGITAL
FILTER
PARALLEL/
SERIAL
INTERFACE
2.5V
REF
REFCAPB
REFCAPA
SERIAL
PARALLEL
REGCAP
2.5V
LDO
REGCAP
2.5V
LDO
AV
CC
AV
CC
DB[15:0]
AD7606
08479-001
Figure 1.
AD7606/AD7606-6/AD7606-4 Data Sheet
Rev. F | Page 2 of 37
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications .................................................................................... 4
Timing Specifications .................................................................. 7
Absolute Maximum Ratings ......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 17
Terminology .................................................................................... 21
Theory of Operation ...................................................................... 22
Converter Details ....................................................................... 22
Analog Input ............................................................................... 22
ADC Transfer Function ............................................................ 23
Internal/External Reference ...................................................... 24
Typical Connection Diagram ................................................... 25
Power-Down Modes .................................................................. 25
Conversion Control ................................................................... 26
Digital Interface .............................................................................. 27
Parallel Interface (
PAR
/SER/BYTE SEL = 0) ......................... 27
Parallel Byte (
PAR
/SER/BYTE SEL = 1, DB15 = 1) .............. 27
Serial Interface (
PAR
/SER/BYTE SEL = 1) ............................ 27
Reading During Conversion ..................................................... 28
Digital Filter ................................................................................ 29
Layout Guidelines ...................................................................... 33
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
4/2020—Rev. E to Rev. F
Change to Features Section ............................................................. 1
Changes to Table 1 ........................................................................... 1
5/2018—Rev. D to Rev. E
Changes to Patent Note, Note 1 ..................................................... 3
Changes to t
CONV
Parameter, Table 3 ............................................. 7
11/2017—Rev. C to Rev. D
Changes to Features Section ........................................................... 1
Changes to Specifications Table Summary ................................... 3
Deleted Endnote 1, Table 1; Renumbered Sequentially .............. 6
Change to Table 6 ........................................................................... 14
Changes to Typical Performance Characteristics Section ........ 17
Changes to Terminology Section ................................................. 21
Changes to Ordering Guide .......................................................... 34
1/2012—Rev. B to Rev. C
Changes to Analog Input Ranges Section ................................... 22
10/2011—Rev. A to Rev. B
Changes to Input High Voltage (V
INH
) and Input Low Voltage
(V
INL
) Parameters and Endnote 6, Table 2 ..................................... 4
Changes to Table 3 ............................................................................ 7
Changes to Table 4 ......................................................................... 11
Changes to Pin 32 Description, Table 6 ...................................... 13
Changes to Analog Input Clamp Protection Section ................ 22
Changes to Typical Connection Diagram Section .................... 25
8/2010—Rev. 0 to Rev. A
Changes to Note 1, Table 2 .............................................................. 6
5/2010—Revision 0: Initial Version