GD32F10x User Manual

Table of Contents

Table of Contents ........................................................................................................... 2

List of Figures ................................ .............................................................................. 19

List of Tables ................................................................................................................ 27

1. System and memory architecture ................................................................ ........ 31

1.1. ARM Cortex-M3 processor ........................................................................................ 31

1.2. System architecture .................................................................................................. 32

1.3. Memory map .............................................................................................................. 37

1.3.1. Bit-banding ............................................................................................................................ 41

1.3.2. On-chip SRAM memory ........................................................................................................ 42

1.3.3. On-chip flash memory overview ........................................................................................... 42

1.4. Boot configuration..................................................................................................... 42

1.5. Device electronic signature ...................................................................................... 43

1.5.1. Memory density information .................................................................................................. 44

1.5.2. Unique device ID (96 bits) .................................................................................................... 44

1.6. System configuration registers ................................................................................ 45

2. Flash memory controller (FMC) ............................................................................ 47

2.1. Overview .................................................................................................................... 47

2.2. Characteristics ........................................................................................................... 47

2.3. Function overview ..................................................................................................... 47

2.3.1. Flash memory architecture ................................................................................................... 47

2.3.2. Read operations ................................................................................................................... 48

2.3.3. Unlock the FMC_CTLx registers........................................................................................... 49

2.3.4. Page erase ............................................................................................................................ 49

2.3.5. Mass erase ........................................................................................................................... 50

2.3.6. Main flash programming ....................................................................................................... 52

2.3.7. Option bytes Erase ............................................................................................................... 53

2.3.8. Option bytes modify .............................................................................................................. 54

2.3.9. Option bytes description ....................................................................................................... 54

2.3.10. Page erase/program protection ............................................................................................ 56

2.3.11. Security protection ................................................................................................................ 56

2.4. Register definition ..................................................................................................... 57

2.4.1. Wait state register (FMC_WS) .............................................................................................. 57

2.4.2. Unlock key register 0(FMC_KEY0) ....................................................................................... 57

2.4.3. Option byte unlock key register (FMC_OBKEY) ................................................................... 58