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MAX3679A Evaluation Kit
Evaluates: MAX3679A
General Description
The MAX3679A evaluation kit (EV kit) is an assembled
demonstration board that provides convenient evalua-
tion of the MAX3679A low-jitter, precision clock genera-
tor. The EV kit includes an on-board 25MHz crystal to
allow immediate testing.
The EV kit includes switches to allow easy selection of
different modes of operation. The reference input and
clock outputs use SMA connectors and are AC-coupled
to simplify connection to test equipment.
Features
S
AC-Coupled I/Os for Ease of Testing
S
Fully Assembled and Tested
S
+3.3V Power-Supply Operation
S
On-Board 25MHz Crystal
Ordering Information
Component List
Component Supplier
19-5173; Rev 0; 2/10
+Denotes lead(Pb)-free and RoHS compliant.
*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Note: Indicate that you are using the MAX3679A when contacting this component supplier.
PART TYPE
MAX3679AEVKIT+ EV Kit
DESIGNATION QTY DESCRIPTION
C1, C3, C4, C5,
C7–C10, C19,
C25–C30, C54
16
0.1FF Q10% ceramic capacitors
(0402)
C2 1
10FF Q10% ceramic capacitor
(0603)
C6, C57–C60 5
0.01FF Q10% ceramic capacitors
(0402)
C22 1
27pF Q10% ceramic capacitor
(0402)
C23 1
33pF Q10% ceramic capacitor
(0402)
C65 1
4.7pF Q10% ceramic capacitor
(0402)
J1, J3, J5 0 Not installed
J2, J48 2 Test points
J4 1 2-pin header, 0.1in centers
J13–J16, J18,
J19, J36, J43
8 SMA connectors
L1 1
2.7FH inductor
R1–R5, R7 6
150I Q5% resistors (0402)
R6, R8, R9 0 Not installed
DESIGNATION QTY DESCRIPTION
R42 1
499I Q1% resistor (0402)
R57 1
49.9I Q1% resistor (0402)
R59 1
10.5I Q1% resistor (0402)
R61 1
36I Q5% resistor (0402)
SW1, SW2,
SW3, SW11
4 SP3T switches
SW4, SW6,
SW9, SW12,
SW13, SW15
6 SPDT switches
TP6, TP7 2 Test points
U1 1
+3.3V, low-jitter crystal to
LVPECL clock generator
(32 TQFN-EP*)
Maxim MAX3679AETJ+
Y1 1
25MHz crystal
NDK EXS00A-AT00429
— 1 Shunt
— 1
PCB: MAX3679A EVALUATION
BOARD+, REV A
SUPPLIER PHONE WEBSITE
NDK America 815-544-7900 www.ndk.com/en
E V A L U A T I O N K I T A V A I L A B L E
MAX3679A Evaluation Kit
Evaluates: MAX3679A
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Quick Start
For evaluation of the MAX3679A, configure the EV kit as
follows:
1) Determine which output is going to be evaluated and
connect to the test equipment through SMA cables.
Be sure not to leave any outputs unterminated (i.e.,
place 50I terminators on all unused outputs).
2) Connect a +3.3V power supply to J48 (VCC) and J2
(GND). Set the current limit to 200mA.
3) If the on-board crystal is used, set IN_SEL to HIGH.
4) Use Table 2 to set the output divider switches to
achieve the output frequency desired.
5) Enable the output under test by setting the related
output-enable switch (Qx_OE) HIGH.
Table 1. Adjustment and Control Descriptions (see Quick Start first)
Table 2. Output Divider Settings
COMPONENT NAME FUNCTION
J4
INDUCTOR
SHUNT
J4 shunts the power-supply inductor. Normal operation is J4 shunted.
SW1 SELB1 SW1 and SW2 set the output divider for the QB outputs. See Table 2 for more information.
SW2 SELB0 SW1 and SW2 set the output divider for the QB outputs. See Table 2 for more information.
SW3 SELA1 SW3 and SW11 set the output divider for the QA outputs. See Table 2 for more information.
SW4 QAC_OE Set HIGH to enable the LVCMOS output, QA_C. Set LOW to disable QA_C.
SW6
BYPASS
Set LOW to bypass the PLL. Set HIGH to engage the PLL. Note that when the PLL is
bypassed the output dividers are automatically set to divide by 1.
SW9 QA_OE Set HIGH to enable LVPECL output QA. Set LOW to force a logic zero at QA.
SW11 SELA0 SW3 and SW11 set the output divider for the QA outputs. See Table 2 for more information.
SW12 QB1_OE Set HIGH to enable LVPECL output QB1. Set LOW to force a logic zero at QB1.
SW13 IN_SEL
Set HIGH to select the crystal as the frequency source. Set LOW to select the REF_IN as the
frequency source.
SW15 QB0_OE Set HIGH to enable LVPECL output QB0. Set LOW to force a logic zero at QB0.
INPUT
NA/NB DIVIDER
OUTPUT FREQUENCY
(25MHz CRYSTAL)
SELA1/SELB1 SELA0/SELB0
LOW LOW ÷2 312.5
HIGH LOW ÷4 156.25
HIGH HIGH ÷5 125
LOW OPEN ÷10 62.5