Effective Date:
PCN Issue Date:
PCN Type:
6/2/2020
9/8/2020
Datasheet
Description of Change
Silicon Labs is pleased to announce the release of revisions to the following documents:
• Si5388/89 Rev A data sheet from document revision 0.8 to document revision 1.0
A detailed description of the changes to the data sheet are summarized in the change impact section of this document.
Customers are encouraged to download the most recent version of CBPro to take advantage of the latest software features and
algorithms. A detailed description of changes for each CBPro release is available at
https://www.silabs.com/documents/public/release-notes/ClockBuilder-Pro-README.pdf.
200602787 Si5388/89 Datasheet Update to
Revision 1.0
Impact on Form, Fit, Function, Quality, Reliability
There is no impact on form, fit, quality or reliability.
Function changes:
Si5388/89 Rev A Data Sheet revision 1.0 changes -
General – Updated typos, spelling, and grammar throughout document. Added references to AccuTime 1588 software where
applicable.
• Updated front page.
• Updated description, Key Features, and Applications.
• Updated block diagram to removed Multi-Synth blocks.
• 1. Feature List.
• Added ITU profiles supported.
• Added 1 PPS LVCMOS input frequency range and 1 Hz output.
• Changed Differential Output Frequency maximum frequency to 718.5MHz.
• Updated programmable loop bandwidth ranges.
• 2. Ordering Guide.
��� Added new grades Si5389E-Axxxxx-GM, Si5389F-Axxxxx-GM, Si5388E-Axxxxx-GM, Si5388F-Axxxxx-GM.
• Added column for AccuTime™ IEEE 1588 Software Support.
• Added Si5389-FMC.
• Added Notes 4 and 5.
• Figure 3.1 Centralized “Pizza Box” Architecure on page 7 updated to show recovered SyncE clock as input to IEEE 1588
DSPLL DCO.
• Figure 3.2 Application Layer Diagram on page 8 updated to replace Si5388-SW with AccuTime.
• 3.1 Standards Compliance.
• Added G.8273.2 (T-BC, T-TSC), ITU-T G.8273.4 (T-BC-P, T-TSC-P).
• Updated 3.3 DSPLL Loop Bandwidth in Standard Input Mode.
• Updated title of 3.4 DSPLL Loop Bandwidth when Locking to 1 PPS.
• Added 3.4.1 Smartlock Feature.
• Changed title of Section 3.5 to 3.5 AccuTime™ Software IEEE 1588 Servo Loop Time Constants (Only Applies to Device
Grades
A/B/C/D).
• Added 3.5.3 Control Average Time Constant.
• 3.6 Modes of Operation.
• Updated to reflect changes made to Figures 3.3 and 3.4.
• Updated 3.6.3 Lock Acquisition when in Standard Input Mode and 1 PPS Input Mode to incorporate IEEE 1588 mode and
Reason for Change
The datasheet was updated to include additional information on the functionality of the device and to clarify existing information.
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1PPS modes that were added.
• Added 3.6.4 Synchronizing to a Master Clock when in IEEE 1588 Mode
• Updated text description of 3.6.5 Locked Mode.
• Updated title of Section 3.6.6 from Holdover Mode to 3.6.6 Standard Input Holdover Mode.
• Updated title of Section 3.6.7 from SyncE Reference Mode IEEE 1588 to PTP Holdover Mode (IEEE 1588 Holdover Mode).
Section was reworded to clarify the language used to describe how the device enters and exits PTP holdover with and without
physical layer assist. Added note to clarify that DSPLL D must be used as PTP DCO when 1 PPS input is used or that DSPLL A
or C can be used as PTP DCO if input frequency is >8 kHz.
• Updated 3.7 Digitally-Controlled Oscillator (DCO) Mode to clarify that DSPLL A, C, or D can be used.
• Revised 3.8 External Reference (XA/XB, REF/REFb) for consistency with similar Silicon Labs products:
• Updated Figure 3.6 External Reference Connections on page 14 to change REFbar to REFb.
• Revised 3.8.1 External Crystal (XA/XB) for consistency with similar Silicon Labs products.
• Updated Figure 3.7 Crystal Resonator Connections on page 15.
• Revised 3.8.2 External Reference (REF/REFb) for consistency with similar Silicon Labs products.
• Updated Figure 3.8 External Reference Connections on page 16.
• Updated Figure 3.9 Si5388/89 DSPLL Input Selection Crosspoint on page 17 to change IN0bar to IN0b, IN1bar to IN1b, and
IN2bar to IN2b.
• Revised 3.9.4 Input Configuration and Terminations for consistency with similar Silicon Labs products.
• Removed "Figure 3.10. Termination of Differential and LVCMOS Input Signals" as this information is available in the
Si5388/89 Reference Manual and is not necessary in the data sheet, and that inputs IN3–IN4 are single-ended only.
• Updated 3.9.5 Hitless Input Switching in Standard Input Mode to add 1 PPS input mode to clarify that in 1588 or 1 PPS mode
since
input to output phase needs to be preserved instead of absorbed.
• Updated 3.9.7 Glitchless Input Switching to add a requirement of ±10 ppm for switching between two inputs in 1 PPS input
mode
and added a note about manual only switching between IN3 and IN4 that and DSPLL D will enter holdover during the transition.
• Updated Figure 3.12 LOS Status Indicators on page 21 to change IN0bar to IN0b, IN1bar to IN1b, and IN2bar to IN2b.
• In 3.9.3 Automatic Input Selection in Standard Input Mode , replaced the word “assert” with ���alarm free”.
• Updated Figure 3.15 Si5388/89 LOL Status Indicators on page 22 to show status indicators for DSPLL B (Si5388/89 dedicated
to REF/REFb inputs only).
• Added 3.10.6.2 LOL Detection in 1 PPS Mode.
• Added 3.10.6.3 LOL Detection in IEEE 1588 Mode.
• Updated 3.10.7 Interrupt Pin (INTRb) to add 1 PPS input mode to the second paragraph.
• Updated 3.10.6 LOL Detection to clarify pin labels and updated Figure 3.15 Si5388/89 LOL Status Indicators on page 22 to
show all DSPLLs with correct pin labels.
• Updated Figure 3.18 DSPLL to Output Driver Crosspoint on page 25 to change all the outputs from OUTxbar to OUTxb.
• Updated Figure 3.19 Generating a 1 Hz Output using the Si5388/89 on page 26 to change all the outputs from OUTxbar to
OUTxb.
• Revised 3.11.3 Output Terminations to serve as a general description of the supported output terminations.
• Removed Figure 3.21. Supported Differential Output Terminations as these figures are available in the Si5388/89 Reference
Manual and not necessary in the data sheet.
• Removed section 3.11.4 Output Signal Formats because it is covered in 3.11 Outputs.
• Updated 3.11.9 Output Disable During LOL to replace reference to “LOL” on the second line to “out of lock”.
• Updated 3.11.13 Output Divider (R) Synchronization to remove the word “hard” from the second line.
• Added 3.11.14 Programmable Phase Offset for 1 PPS Output.
• Updated 3.13 In-Circuit Programming to replace "registers" with “a boot record” in the last sentence of the section.
• Updated Table 5.2 DC Characteristics on page 32.
• Core Supply Current, Symbol IDDA, changed the test condition to Si5389 and Si5388 for both IEEE 1588 Mode and
Standard Input Mode.
• Control/Status Supply Current, Symbol IDDIO, changed VDDIO = 3.3 V typical value from 8.75 to 9 mA and changed VDDIO
= 1.8 V typical value from 6.5 to 7 mA to allow for margin.
• Rounded up the Typ and Max values of Total Power Dissipation to the second digit to allow for margin.
• Note 1 Test Condition changed from “8 x 2.5 V LVDS outputs enabled @156.25 MHz. IEEE 1588 mode enabled on DSPLL
D. Excludes power in termination resistors” to “Test configuration: 3 x 3.3 V, 156.25 MHz LVDS; 1 x 3.3 V, 500 MHz LVDS; 1 x
3.3 V LVCMOS, 1 PPS. IEEE 1588 mode enabled on DSPLL D. Excludes power in termination resistors”.
• Note 2 removed “DSPLL D configured for free-run".
• Updated Table 5.3 Input Clock Specifications on page 33.
• Updated table to match similar terminology to Input names and Test Conditions.
• Added Note 4 to title.
• Section LVCMOS / Pulsed CMOS DC-Coupled Input Buffer (IN0, IN1, IN2):
• Added Note 5 to Input Voltage.
• Updated Input Voltage VIH for Standard CMOS input and added a new VIH for Non-Standard CMOS and Pulsed CMOS
Input.
• Section LVCMOS DC-Coupled Input Buffer (IN3, IN4):
• Added Note 5 to Input Voltage VIL max spec and to VIH min spec.
• Notes Section:
• Changed text of Note 2 from “Imposed for jitter performance” to “Recommended for specified jitter performance. Jitter
performance could degrade if the minimum slew rate specification is not met (see the Si5388/89 Reference Manual).
• Added Note 4.
• Added Note 5.
• Updated Table 5.4 Control Input Pin Specifications on page 35.
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