Teledyne e2v Semiconductors SAS 2019
EV8AQ160
QUAD ADC
Datasheet DS0846
Whilst Teledyne e2v Semiconductors SAS has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the
consequences of any use thereof and also reserves the right to change the specification of goods without notice. Teledyne e2v Semiconductors SAS accepts no
liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of the devices in accordance with
information contained herein.
Teledyne e2v Semiconductors SAS, avenue de Rochepleine 38120 Saint-Egrève, France Holding Company: Teledyne e2v Semiconductors SAS
Telephone: +33 (0)4 76 58 30 00
Contact Teledyne e2v by e-mail: hotline-bdc@teledyne-e2v.com or visit www.teledyne-e2v.com for global sales and operations centres
MAIN FEATURES
• Quad ADC with 8-bit Resolution
– 1.25 Gsps Sampling Rate in Four-channel Mode
– 2.5 Gsps Sampling Rate in Two-channel Mode
– 5 Gsps Sampling Rate in One-channel Mode
– Built-in four-by-four Crosspoint Switch
• 2.5 GHz Differential Symmetrical Input Clock Required
• ADC Master Reset (LVDS)
• Double Data Rate Output Protocol
• LVDS Output Format
• Digital Interface (SPI) with Reset Signal
– Selectable 1:1 or 1:2 Demultiplexed Outputs
– Channel Mode Selection
– 500 mVpp or 625 mVpp Analog Input (Differential AC or
DC
Coupled)
– Selectable Bandwidth (Four Available Settings)
– Gain Control (±18%)
– Offset Control (±50 mV)
– Phase Control (±14 ps Range)
– Standby Mode (Full or Partial)
– Binary or Gray Coding Selection
–Test Mode
• Power Supplies: 3.3V and 1.8V (Outputs), 1.8V (Digital)
• Power Dissipation: 4.2W Total (1:1 DMUX Mode)
• EBGA380 Package (RoHS, 1.27 mm Pitch)
PERFORMANCE
• Selectable Full Power Input Bandwidth (–3 dB) up to 2 GHz
(4-/2-/1-channel modes)
• Channel-to-channel Isolation: >60 dB
• Four-channel Mode (Fsampling = 1.25 Gsps, –1 dBFS)
– Fin = 100 MHz: ENOB = 7.5 bit, SFDR = 58 dBc,
SNR = 46.5 dBc, DNL = ±0.18 LSB, INL = ±0.4 LSB
– Fin = 620 MHz: ENOB = 7.3 bit, SFDR = 56 dBc,
SNR = 45 dBc
• Two-channel Mode (Fsampling = 2.5 Gsps, –1 dBFS)
– Fin = 100 MHz: ENOB = 7.5 bit, SFDR = 58 dBc,
SNR = 46 dBc, DNL = ±0.14 LSB, INL = ±0.35 LSB
– Fin = 620 MHz: ENOB = 7.2 bit, SFDR = 56 dBc,
SNR = 44.5 dBc
• One-Channel Mode (Fsampling = 5 Gsps,
Fin = 100 MHz, –1 dBFS)
– Fin = 100 MHz: ENOB = 7.4 bit, SFDR = 58 dBc,
SNR = 46 dBc, DNL = ±0.12 LSB, INL = ±0.27 LSB
– Fin = 620 MHz: ENOB = 7.1 bit, SFDR = 56 dBc,
SNR = 44 dBc
• BER: 10
–16
at Full Speed
SCREENING
• Temperature Range for Packaged Device
• Commercial C Grade: 0°C < T
amb
< 70°C
Applications
• High-speed Oscilloscopes
• High-Speed Data Acquisition
• High-Speed Test Instrumentation
• Automatic Test Equipment
• High Energy Physics
0846K–BDC–10/19
2
0846K–BDC–10/19
EV8AQ160
Teledyne e2v Semiconductors SAS 2019
1. BLOCK DIAGRAM
Figure 1-1. Simplified Block Diagram
2. DESCRIPTION
The Quad ADC is constituted by four 8-bit ADC cores which can be considered independently (four-
channel mode) or grouped by two cores (two-channel mode with the ADCs interleaved two by two or
one-channel mode where all four ADCs are all interleaved).
All four ADCs are clocked by the same external input clock signal and controlled via an SPI (Serial
Peripheral Interface). An analog multiplexer (cross-point switch) is used to select the analog input
depending on the mode the Quad ADC is used.
The clock circuit is common to all four ADCs. This block receives an external 2.5 GHz clock (maximum
frequency) and preferably a low jitter symmetrical signal. In this block, the external clock signal is then
divided by two in order to generate the internal sampling clocks:
• In four-channel mode, the same 1.25 GHz clock is directed to all four ADC cores and T/H
• In two-channel mode, the in-phase 1.25 GHz clock is sent to ADC A or C and the inverted 1.25 GHz
clock is sent to ADC B or D, while the analog input is sent to both ADCs, resulting in an interleaved
mode with an equivalent sampling frequency of 2.5 Gsps
• In one-channel mode, the in-phase 1.25 GHz clock is sent to ADC A while the inverted 1.25 GHz clock
is sent to ADC B, the in-phase 1.25 GHz clock is delayed by 90
° to generate the clock for ADC C and
the inverted 1.25 GHz clock is delayed by 90° to generate the clock for ADC D, resulting in an
interleaved mode with an equivalent sampling frequency of 5 Gsps
Several adjustments for the sampling delay and the phase are included in this clock circuit to ensure a
proper phase relation between the different clocks generated internally from the 2.5 GHz clock.
Clock
Buffer
+
Selection
+
SDA
LVDS Buffers
1:1 or 1:2 DMUX
T/H
8-bit
1.25 Gsps
ADC core
Analo g MUX
(Cross Point Swit ch)
Serial
Peripheral
Interface
Offset
Gain
2.5 GHz
Clock
8-bit
1.25 Gsps
ADC core
8-bit
1.25 Gsps
ADC core
8-bit
1.25 Gsps
ADC core
LVDS Buffers
1:1 or 1:2 DMUX
LVDS Buffers
1:1 or 1:2 DMUX
LVDS Buffers
1:1 or 1:2 DMUX
Gain GainGain
T/H T/H T/H
Offset
Offset Offset
Phase PhasePhase Phase