PAC5223 User Guide
Power Application Controller
TABLE OF CONTENTS
1. Styles and Formatting Conventions................................................................................................................. 24
1.1. Overview.................................................................................................................................................. 24
1.2. Number Representation........................................................................................................................... 24
1.3. Formatting Styles..................................................................................................................................... 24
2. Memory and Register Map............................................................................................................................... 25
2.1. Memory Map............................................................................................................................................ 25
2.2. Register Map............................................................................................................................................ 26
3. Information Block............................................................................................................................................. 39
3.1. Register.................................................................................................................................................... 39
3.1.1. Register Map.................................................................................................................................... 39
3.1.2. ROSC11........................................................................................................................................... 39
3.1.3. ADCGAIN......................................................................................................................................... 39
3.1.4. ADCOFF.......................................................................................................................................... 39
3.1.5. FTTEMP........................................................................................................................................... 40
3.1.6. TEMPS............................................................................................................................................. 40
3.1.7. CLKREF........................................................................................................................................... 40
3.1.8. PACIDR............................................................................................................................................ 40
3.2. Details of Operation................................................................................................................................. 40
3.2.1. Overview.......................................................................................................................................... 40
4. System Clock Control....................................................................................................................................... 41
4.1. Register.................................................................................................................................................... 41
4.1.1. Register Map.................................................................................................................................... 41
4.1.2. CCSCTL........................................................................................................................................... 41
4.1.3. PLLCTL............................................................................................................................................ 42
4.1.4. OSCCTL.......................................................................................................................................... 42
4.1.5. XTALCTL.......................................................................................................................................... 42
4.2. Details of Operation................................................................................................................................. 43
4.2.1. Block Diagram.................................................................................................................................. 43
4.2.2. Configuration.................................................................................................................................... 43
4.2.3. ROSC............................................................................................................................................... 44
4.2.4. CLKREF........................................................................................................................................... 44
4.2.5. XTAL................................................................................................................................................ 44
4.2.6. EXTCLK........................................................................................................................................... 44
4.2.7. PLL................................................................................................................................................... 44
4.2.8. FRCLK............................................................................................................................................. 45
4.2.9. FCLK................................................................................................................................................ 45
4.2.10. HCLK............................................................................................................................................. 45
4.2.11. ACLK.............................................................................................................................................. 45
4.2.12. Clock Gating................................................................................................................................... 45
5. Watchdog Timer............................................................................................................................................... 46
5.1. Register.................................................................................................................................................... 46
5.1.1. Register Map.................................................................................................................................... 46
5.1.2. WDTCTL.......................................................................................................................................... 46
5.1.3. WDTCDV......................................................................................................................................... 47
5.1.4. WDTCTR......................................................................................................................................... 47
5.2. Details of Operation................................................................................................................................. 48
5.2.1. Block Diagram.................................................................................................................................. 48
5.2.2. Configuration.................................................................................................................................... 48
5.2.3. Watchdog Timer............................................................................................................................... 48
5.2.4. Access WDT Registers.................................................................................................................... 48
5.2.5. WDT Clock Setting........................................................................................................................... 48
- 2 - Rev 18‒March 4, 2018