Si5388/89 Data Short
Network Synchronizer Clocks for IEEE
TM
1588v2
The multi-PLL Si5388/89 network synchronizer clocks with internal servo algorithm
paired with the Si5388-SW protocol stack offers the most integrated IEEE 1588 solution
in the industry targeting applications that use a centralized “pizza box��� architecture. The
Si5388/89 offers three DSPLLs that are capable of both IEEE 1588 high resolution DCO
control or G.8262 SyncE clock filtering. The Si5388/89 also has an internal IEEE 1588
servo algorithm that processes incoming time stamps and then automatically controls the
DCO at a 1ppt resolution – all in a 9x9mm package. The unique design of the Si5388/89
includes a dedicated TCXO/OCXO reference interface with built-in jitter cleaning that will
not degrade the output performance of the clock. The Si5388/89 synchronizer clock with
Si5388-SW protocol stack is a complete IEEE 1588 and SyncE solution.
Applications
•
Frequency synchronization in packet networks ITU-T G.8261
• Synchronous Ethernet (SyncE) ITU-T G.8262 and G.8262.1
• Telecom Boundary Clock and Telcom-Time Slave Clock (T-BC, T-TSC) ITU-T G.
8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813 network synchronization
KEY FEATURES
• Up to three independent DSPLLs in a
single IC supporting flexible SyncE/IEEE
1588 and SETS architectures
•
Embedded IEEE 1588 servo loop
processing
• IEEE 1588 software protocol stack
• Input frequency range:
• External crystal: 48–54 MHz
• REF clock: 5–250 MHz
• Differential clock: 8 kHz–750 MHz
• LVCMOS clock: 8 kHz–250 MHz
• Output frequency range:
• Differential: 1 Hz, 100 Hz–750 MHz
• LVCMOS: 1 Hz, 100 Hz–250 MHz
• Ultra-low jitter: 90 fs rms typ
DSPLL
A
Si5388/89
REF
XB XA
XTAL
OCXO/
TCXO
REF
IN2
IN1
IN0
÷FRAC
÷FRAC
÷FRAC
DSPLL
D
IN4
IN3
DSPLL
C
OUT6
OUT5
OUT2
OUT4
OUT3
OUT1
OUT0
OUT7
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
Multi-
Synth
Multi-
Synth
Si5389
Si5388
OSC
Control/
Status
IEEE 1588
Servo Loop Processor
Serial I/F and Flash NVM
silabs.com | Building a more connected world. Rev. 0.1
1. Pin Descriptions
GND
Pad
VDD
OUT4
VDDO4
OUT3
VDDA
VDDO3
RSTb
VDD
OUT2
OUT1
OUT1b
VDDO1
RSVD
OUT0b
OUT0
IN4
VDDIO
SCLK
RSVD
VDDO7
MOSI
CSb
VDDA
SPI_EN
RSVD
IN1
IN1b
OEb
X1
XA
XB
X2
LOL_Ab
VDDA
IN2
IN2b
VDDIO
BLMDb
IN3
INTRb
IN0b
IN0
REFb
REF
VDD
OUT7
OUT7b
OUT6
OUT6b
LOL_Db
VDDO6
OUT5
OUT5b
VDDO5
LOL_Cb
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
MISO
Si5389 64-LGA
Top View
OUT3b
OUT4b
OUT2b
VDDO2
DECOUPLE
RSVD
VDDO0
LOL_REFb
Figure 1.1. Si5389 Pins
GND
Pad
VDD
OUT4
VDDO4
OUT3
VDDA
VDDO3
RSTb
VDD
OUT2
OUT1
OUT1b
VDDO1
RSVD
OUT0b
OUT0
IN4
VDDIO
SCLK
RSVD
VDDO7
MOSI
CSb
VDDA
SPI_EN
RSVD
IN1
IN1b
OEb
X1
XA
XB
X2
LOL_Ab
VDDA
IN2
IN2b
VDDIO
BLMDb
IN3
INTRb
IN0b
IN0
REFb
REF
VDD
OUT7
OUT7b
OUT6
OUT6b
LOL_Db
VDDO6
OUT5
OUT5b
VDDO5
RSVD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
MISO
Si5388 64-LGA
Top View
OUT3b
OUT4b
OUT2b
VDDO2
DECOUPLE
RSVD
VDDO0
LOL_REFb
Figure 1.2. Si5388 Pins
Si5388/89 Data Short
Pin Descriptions
silabs.com | Building a more connected world. Rev. 0.1 | 2