IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 8, AUGUST 2008 1807

A 10-kV Large-Area 4H-SiC Power DMOSFET

With Stable Subthreshold Behavior

Independent of Temperature

Robert S. Howell, Member, IEEE, Steven Buchoff, Stephen Van Campen, Member, IEEE,

Ty R. McNutt, Member, IEEE, Andris Ezis, Senior Member, IEEE, Bettina Nechay, Member, IEEE,

Christopher F. Kirby, Member, IEEE, Marc E. Sherwin, Member, IEEE,

R. Chris Clarke, Fellow, IEEE, and Ranbir Singh, Member, IEEE

Abstract—This paper presents the development and demon-

stration of large-area 10-kV 4H-SiC DMOSFETs that maintain

a classically stable low-leakage normally off subthreshold char-

acteristic when operated at ≤ 200

◦

C. This is achieved by an

additional growth (epitaxial regrowth) of a thin epitaxial layer

on top of already implanted p-well regions in conjunction with a

O-based gate oxidation process. Additionally, the design space

of the DMOSFET structure was explored using analytical and

numerical modeling together with experimental veriﬁcation. The

resulting 0.15-cm

active 0.43-cm

die DMOSFET with 10-kV

breakdown provides I

= 8 A at a gate ﬁeld of 3 MV/cm, along

with a subthreshold current at V

= 0 V that decreases from

1 µA (6.7 µA/cm

)at25

◦

C to 0.4 µA (2.7 µA/cm

) at 200

◦

Index Terms—Power MOSFETs, power switching, silicon

carbide, subthreshold behavior.

I. I NTRODUCTION

F GREAT interest for high-voltage (10+ kV) switching

applications is the 4H-SiC DMOSFET because it com-

bines the high-breakdown low speciﬁc on-resistance of the

4H-SiC drift region with the majority carrier operation of the

MOSFET, thereby accruing both low switching losses and

the uniform current distribution needed for device paralleling.

These attributes have made the 4H-SiC DMOSFET attractive

as a potential candidate for insertion into future 10+ kV power

switching architectures [1]. The lower switching losses of the

SiC DMOSFET allow the architectures to be designed around

higher frequencies (≥ 20 kHz), substantially reducing the

overall system size and weight of solid-state power switching

applications.

Signiﬁcant effort has been made in the development of 4H-

SiC DMOSFETs, primarily in the 1+-kV range, including

work on optimizing the design of the DMOSFET structure [2].

However, because of their thinner drift layers and low speciﬁc

Manuscript received November 29, 2007; revised May 1, 2008 and May 21,

2008. This work was supported by Ofﬁce of Naval Research Contract N00014-

05-C-0203 under contract monitor Dr. Harry Dietrich. The review of this paper

was arranged by Editor J. Cooper.

R. S. Howell, S. Buchoff, S. Van Campen, T. R. McNutt, A. Ezis, B. Nechay,

C. F. Kirby, M. E. Sherwin, and R. C. Clarke are with Northrop Grumman

Corporation, Linthicum, MD 21090 USA (e-mail: rs.howell@ngc.com).

R. Singh is with GeneSiC Semiconductor Inc., Dulles, VA 20166 USA.

Color versions of one or more of the ﬁgures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identiﬁer 10.1109/TED.2008.928204

on-resistances, these lower voltage SiC DMOSFETs are smaller

in area and have different equivalent circuit design considera-

tions than used with 10-kV SiC DMOSFETs. The 10-kV SiC

DMOSFETs have recently been scaled up in current output,

with die sizes increasing from 0.11 cm

(0.0476-cm

active

area) to 0.3 cm

(0.15-cm

active area) reported, capable of

5–10 A at room temperature [ 3], [4]. In addition to these useful

improvements in blocking voltage and

ON-state current, it is

essential that DMOSFETs demonstrate a stable subthreshold

characteristic over the projected operating temperature range

(≤ 200

◦

C). This is critical in order to satisfy the need for both a

normally off device and a device with an

OFF-state leakage that

does not compromise its blocking voltage at higher tempera-

tures. The large-area SiC DMOSFETs reported in the literature,

which have provided their subthreshold behavior as a function

of temperature, have tended to become normally on or have

excessive

OFF-state leakage when operated at high (> 150

◦

temperatures due to an apparent temperature-dependent ﬁxed

charge voltage shift in their subthreshold characteristic [5].

In order to create a viable 10+-kV SiC MOSFET, a robust

process is required that achieves a sustainable yield of large-

area devices that have low-leakage normally off subthreshold

characteristics above 150

◦

C. In this paper, we report on the

successful development and demonstration of such a large-area

10+-kV SiC MOSFET process.

II. D

ESIGN CONSIDERATIONS

The fabrication of 4H-SiC DMOSFETs in the 10+-kV range

poses particular challenges resulting from the limitations of

currently available SiC material quality and the required thick

(∼100 µm) drift region to achieve 10+ kV, competing with the

need for large-area devices. As the power switching modules

that would use these 10-kV devices are speciﬁed to carry over

a hundred amperes, even paralleling several DMOSFET parts

in each module still requires each DMOSFET die to have a

large active area in addition to a large area devoted to junction

termination extension (JTE) that allows 10+-kV breakdown.

For example, at room temperature, a 100-µm drift region doped

at 5 × 10

−3

that is appropriate for 10-kV blocking will

have a speciﬁc on-resistance of 133 mΩ · cm

. Thus, consider-

ing the drift resistance alone, a 10-A part in a package capable

of removing 750 W/cm

of waste heat from the part would

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1808 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 8, AUGUST 2008

require at least an active area of 0.133 cm

, and when the

effects of self-heating at elevated power levels are considered,

an even larger active area would be required to maintain the

10-A current level and thereby compensate for the i ncreased

drift resistance associated with the inverse relationship between

carrier mobility and temperature. However, using 0.133-cm

active area as a baseline and if the active area is a square with

a lateral JTE length of 500 µm, the ﬁnal die size would then

be 0.216 cm

. Large die areas such as this suffer from a pro-

nounced sensitivity to the defect density in the 4H-SiC material,

creating substantial challenges in developing robust processes

that have useful yields of 10-kV devices. This has been pre-

viously illustrated even at the 1-kV level, as 1200-V 4H-SiC

vertical JFETs have been reported to have a decrease in their ob-

served breakdown voltage with respect to the theoretical max-

imum allowed by the drift conditions, from 93% for VJFETs

with 1.23 × 10

−3

-cm

active areas to 91% for 0.068-cm

active areas [6], [7].

These problems are in addition to the requirement that

4H-SiC MOSFETs maintain normally off behavior as a func-

tion of temperature. If, as has been observed [5], the subthresh-

old behavior shifts toward a normally

ON-state as a function

of increasing operating temperature, even if the device remains

normally off (i.e., a positive threshold voltage), the increase

OFF-state leakage associated with the shifting subthreshold

region can dramatically reduce the breakdown voltage of the

device independent of the JTE design.

In order to ameliorate these issues, a successful large-area

10+-kV MOSFET is required to employ a higher degree of

margin in the design rules and process techniques than used

for lower voltage material. An example of this is in the choice

of drift thickness and doping. Assuming the adoption of a

punchthrough structure, a theoretical 10-kV breakdown could

be achieved with a 75-µm-thick drift doped at 9×10

−3

with a speciﬁc on-resistance of only 57 mΩ · cm

, which is

less than half the speciﬁc on-resistance of drifts actually used

in 10-kV devices. The reason for t he difference is twofold:

1) The defects inherent in the material reduce the achievable

breakdown voltage of the device, a problem exacerbated for

larger devices which contain more defects, and 2) variations

in thickness and doping of epitaxially grown ﬁlms necessitate

conservative speciﬁcations for these ﬁlms in order to ensure that

the resulting drift layer will be capable of blocking the desired

voltage.

Fig. 1 shows an analytical model of the breakdown for a

4H-SiC punchthrough drift structure as a function of thickness

and doping level. Given the presence of defects and limitations

on JTE design due to process variance, an at least 25% margin

above the 10-kV range is desirable to maximize the likelihood

of achieving 10-kV MOSFETs with reasonable yield. Addition-

ally, the epitaxial vendor was only able to specify doping within

±25% and thickness within ±10% for this region of thick, low

doped drift. Thus, Fig. 1 highlights the resulting region for a

nominally 100-µm layer doped at 5 × 10

−3

, becoming

90–110 µm and 3.75 × 10

−6.25 × 10

−3

based on these

error bars, respectively, and shows that the minimum break-

down for this process space is 12.5 kV, incorporating the desired

25% margin above 10 kV.

Fig. 1. Analytical model of breakdown voltage for a SiC punchthrough drift

region nominally doped at 45 × 10

−3

(±25%) and 100 µm(±10%)

thick, appropriate for 10-kV operation with a 25% margin.

Having deﬁned an appropriate drift region thickness and

doping to meet the OFF-state blocking, the ON-state properties

still require optimization, involving both the MOS channel

characteristics ( mobility, threshold voltage, etc.) and the physi-

cal layout of the device. Unlike 1+-kV SiC DMOSFETs which

are very sensitive to channel resistance and channel mobility,

the higher resistance of the drift in 10-kV DMOSFETs makes

the channel resistance and mobility much less of a contributor

to the total device on-resistance. DMOSFETs of 10 kV do,

however, share a common sensitivity to threshold voltage and

subthreshold stability as a function of temperature. It has been

observed, however, that SiC MOS channels of higher mobility

and lower resistance, which are formed using an NO oxidation

method, have low and even normally on threshold voltages, as

well as subthreshold characteristics that shift toward a leaky

state as temperature increases [5]. For this reason, a twofold

approach to stabilizing the threshold voltage as a function of

temperature was taken. First, the channel performance was

improved using an epitaxial regrowth (performed at Northrop

Grumman Corporation) above the implanted p-well region in

conjunction with a N

O gate oxidation process. The use of

a similar epitaxial regrowth layer above the implanted p-well

has previously been shown to improve the channel resistance

[8], [9] and, in this paper, is shown to also improve the sub-

threshold/temperature characteristics. The second aspect was to

design and fabricate an array of small-area DMOSFETs in order

to pragmatically explore the device geometry design space.

III. E

XPERIMENTAL DETERMINATION OF CHANNEL

PROCESS AND DEVICE GEOMETRIES

Efforts to explore the 10-kV DMOSFET geometry design

space and the channel process were performed in parallel, to

be combined together in an optimized large-area device after

obtaining the results from both experimental thrusts. The design

space optimization focused on the pitch of the DMOSFET

cell, examining gate length, JFET spacing, and N+ source

contact length effects on the device performance. Fig. 2 shows

a representative cross section of the DMOSFET, with the var-

ious regions of interest being highlighted. A s hort gate length

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