Figure

: Anode/Gate designs of SiC GTO

thyristors fabricated on the same wafer – A

fine Involute, Hex, Coarse Involute and

raster.

Large Area >8 kV SiC GTO Thyristors with innovative Anode-Gate

designs

Siddarth G. Sundaresan, Hany Issa, Deepak Veereddy

and Ranbir Singh

GeneSiC Semiconductor, Inc., 43670 Trade Center Pl, Suite 155, Dulles, VA 20166, USA

sid@genesicsemi.com

Keywords: Silicon Carbide, GTO, Thyristors, High-Voltage, High-Current, Pulsed Power.

Abstract. This study is focused on the design and fabrication of large-area (4.1x4.1 mm

and

8.2x8.2 mm

), 8.1 kV 4H-SiC GTO Thyristors. The anode and gate fingers of Thyristors were

designed with involute, cellular or hexagonal patterns. Forward blocking voltages as high as 8106 V

and On-state voltage drop (Von) and differential specific on-resistance (R

on,sp

) as low as 3.8 V and 6

mΩ-cm

at 100 A/cm

were measured on these devices. About 59% of 4.1 x4.1 mm

and 29% of

8.2x8.2 mm

Thyristors blocked voltages in excess of 6 kV. Detailed investigations revealed the

impact of different anode/gate finger geometries on the device characteristics. Preliminary pulsed

power characterization of the GTO Thyristors was also performed.

Introduction

There is a strong interest for the development of a high voltage, high current, high frequency Silicon

Carbide (SiC) based switches for utility applications. These applications demand high frequency

power conversion with an order of magnitude higher power levels at an order of magnitude higher

frequency as compared to what is achievable with contemporary silicon power devices. As

compared to unipolar devices like JFETs and MOSFETs, bipolar-mode switches like Gate Turn-Off

(GTO) Thyristors offer low conduction losses in >6 kV ratings, due to high level of minority carrier

injection into the low doped voltage blocking region [1-3]. This paper focuses on large area

(4.1x4.1 mm

and 8.2x8.2 mm

) > 8 kV SiC GTO Thyristors recently designed and fabricated at

GeneSiC.

Epilayer and Device Design

Epilayer Design The first step in the (N

P-NP

) Thyristor epilayer design was to determine the

doping and thickness of the voltage blocking p

layer. Direct integration of the ionization integral

was performed to simulate the breakdown voltages for different epilayer thickness/doping

combinations. The ideal unipolar parallel plane breakdown voltage for an epilayer thickness of 60

µm was simulated to be 9700 V. The other layers

were subsequently designed for optimizing the GTO

Thyristor device characteristics.

Device Design/Layout The anode/gate fingers of the

GTO Thyristors were inter-digitated in cellular,

involute or hexagonal patterns (see Fig. 1) to

determine their effect on on-state and turn-off

capability. For each layout geometry, the anode and

gate finger widths were also varied to examine their

impact on the device performance. In this study,

GTO Thyristors with an active area of 4.1x4.1 mm

and 8.2x8.2 mm

were used. A summary of the

different Gate/Anode designs investigated in this

study is given in Table 1. A combination of mesa and

junction termination extension (JTE) based edge

termination strategies were employed for optimizing

the forward blocking characteristics.

Figure 2: Cross-sectional SEM image depicting the

two-level metallization scheme incorporating a

novel planarization/gap-fill process

Table 1: Summary of various anode-gate variations investigated in the first batch of GeneSiC’s GTO

Device ID Pattern Anode width (µm) Gate width (µm)

Involute

117

Involute

117

Cellular

Hexagonal

Device Fabrication

Reactive ion etching (RIE) of the SiC was

performed for isolating the individual devices, and

for providing gate access trenches for connecting

the gate fingers. The channel-stop, gate and JTE

implantations were then performed by using various

masking techniques. High-temperature annealing at

1690 °C was performed to heal the implant-induced

lattice damage and to electrically activate the

implanted dopants. Next, ohmic contacts to the

anode and gate fingers were formed by metal

deposition followed by rapid thermal annealing. A

thick overlayer metal was then patterned on top of

the ohmic contacts to decrease the lateral resistance

along the gate fingers. A two-level metallization

process incorporating a novel planarization/ gap-

fill scheme was developed and implemented to

connect the anode and gate fingers of the GTO Thyristors. A cross-sectional SEM image, depicting

the two-level metallization scheme is shown in Fig. 2.

Device Characterization

On-state and blocking characteristics An automated test system was used to investigate the on-

state and forward blocking characteristics of the Thyristors. The devices were turned on by

increasing the gate current in 10 mA steps until the device latched on, while keeping the V

bias

fixed at 5 V. Representative forward I-V curves measured on a 4.1x 4.1 mm

GTO thyristor are

shown in Figure 3.

(a) (b)

Figure 3: Turn-on I-V characteristics measured on a representative 4.1 x 4.1 mm

GTO Thyristor at (a) low

currents and (b) high currents