ATSAMR30M18A

SAMR30 IEEE® 802.15.4™ Sub-1GHz Module Datasheet

Introduction

The ATSAMR30M18A is an IEEE

802.15.4

™

-2003/2006/2011 compliant RF module for the sub-1GHz

ISM bands such as 780 MHz (China), 868 MHz (Europe) and 915 MHz (North America), optimized for

low-power applications. This module combines the SAMR30E18A SiP (System in Package), 16 MHz

crystal oscillator, discrete balun, lumped element harmonic reject filter and required RF shielding in a

compact 12.7mm x 11.0mm design. The module as implemented on the Xplained Pro development board

has passed regulatory approvals with chip antenna or SMA connectorized monopole antenna.

This datasheet provides only a brief overview of necessary sections of the module. For a detailed

description of each peripheral, refer to the ATSAMR30E18A datasheet.

Features

• Processor

– ARM

Cortex

-M0+ CPU running at up to 48 MHz

• Single-cycle hardware multiplier

• Micro Trace Buffer (MTB)

• Memories

– 256 KB in-system self-programmable Flash

– 32 KB SRAM

�� 8 KB low-power RAM

• System

– Power-on Reset (POR) and Brown-out Detection (BOD)

– Internal clock option with 48 MHz Digital Frequency Locked Loop (DFLL48M) and 48 MHz to 96

MHz Fractional Digital Phase Locked Loop (FDPLL96M)

– External Interrupt Controller (EIC)

– Up to 14 external interrupts

– One non-maskable interrupt

– Two-pin Serial Wire Debug (SWD) programming, test and debugging interface

• Low Power

– Idle and Standby Sleep modes

– Sleep walking peripherals

• Integrated Ultra-Low Power Transceiver for 700/800/900 MHz ISM Band:

– Chinese WPAN band from 779 to 787 MHz

– European SRD band from 863 to 870 MHz

– North American ISM band from 902 to 928 MHz

Datasheet

DS70005384A-page 1

– Japanese band from 915 to 930 MHz

• Direct Sequence Spread Spectrum with Different Modulation and Data Rates:

– BPSK with 20 and 40 kb/s, compliant to IEEE 802.15.4-2003/2006/2011

– O-QPSK with 100 and 250kb/s, compliant to IEEE 802.15.4-2006/2011

– O-QPSK with 200, 400, 500, and 1000kb/s PSDU data rate

– Industry-leading link budget:

• RX sensitivity up to -105 dBm

• TX output power up to +8.7 dBm

– Hardware-assisted MAC:

• Auto-Acknowledge

• Auto-Retry

• CSMA-CA and Listen Before Talk (LBT)

• Automatic address filtering and automated FCS check

– Special 802.15.4-2011 hardware support:

• FCS computation and Clear Channel Assessment

• RSSI measurement, Energy Detection and Link Quality Indication

– 128 Byte TX/RX Frame Buffer

– Integrated 16 MHz Crystal Oscillator (external crystal is not needed)

– Fully integrated, fast settling transceiver PLL to support frequency hopping

– Hardware Security (AES, True Random Generator)

• Peripherals

– 16-channel Direct Memory Access Controller (DMAC)

– 12-channel event system

– Up to three 16-bit Timer/Counters (TC), including one low-power TC(TC4), each configurable as:

• 16-bit TC with two compare/capture channels

• 8-bit TC with two compare/capture channels

• 32-bit TC with two compare/capture channels, by using two TCs

– Two 24-bit and one 16-bit Timer/Counters for Control (TCC), with extended functions:

• Up to four compare channels with optional complementary output

• Generation of synchronized pulse width modulation (PWM) pattern across port pins

• Deterministic fault protection, fast decay and configurable dead-time between

complementary output

• Dithering that increase resolution with up to 5 bit and reduce quantization error

– 32-bit Real Time Counter (RTC) with clock/calendar function

– Watchdog Timer (WDT)

– CRC-32 generator

– One full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface

• Embedded host and device function

• Eight endpoints

– Up to two Serial Communication Interfaces (SERCOM), each configurable to operate as either:

• USART with full-duplex or single-wire half-duplex configuration

• I

C up to 3.4 MHz

ATSAMR30M18A

Datasheet

DS70005384A-page 2