Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core
User Guide
2016.06.23
UG-01155
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The Altera IOPLL megafunction IP core allows you to configure the settings of Arria
®
10 I/O PLL.
Altera IOPLL IP core supports the following features:
• Supports six different clock feedback modes: direct, external feedback, normal, source synchronous,
zero delay buffer, and LVDS mode.
• Generates up to nine clock output signals for the Arria 10 device.
• Switches between two reference input clocks.
• Supports adjacent PLL (adjpllin) input to connect with an upstream PLL in PLL cascading mode.
• Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.
• Supports PLL dynamic phase shift.
Related Information
• Introduction to Altera IP Cores
Provides more information about the Altera IP cores and the parameter editor.
• Operation Modes on page 9
• Output Clocks on page 10
• Reference Clock Switchover on page 10
• PLL-to-PLL Cascading on page 11
• Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide Archives on page 12
Provides a list of user guides for previous versions of the Altera IOPLL IP core.
Device Family Support
The Altera IOPLL IP core only supports the Arria 10 device family.
Altera IOPLL IP Core Parameters
The Altera IOPLL IP core parameter editor appears in the PLL category of the IP Catalog.
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Altera IOPLL IP Core Parameters - PLL Tab
Table 1: Altera IOPLL IP Core Parameters - PLL Tab
Parameter Legal Value Description
Device Family Arria 10 Specifies the device family.
Component — Specifies the targeted device.
Speed Grade — Specifies the speed grade for targeted device.
PLL Mode Integer-N PLL Specifies the mode used for the Altera IOPLL IP core. The
only legal selection is Integer-N PLL. If you need a fractional
PLL, you must use the Arria 10 FPLL IP core.
Reference Clock
Frequency
— Specifies the input frequency for the input clock, refclk, in
MHz. The default value is 100.0 MHz. The minimum and
maximum value is dependent on the selected device.
Enable Locked Output
Port
Turn on or
Turn off
Turn on to enable the locked port.
Enable physical output
clock parameters
Turn on or
Turn off
Turn on to enter physical PLL counter parameters instead of
specifying a desired output clock frequency.
2
Altera IOPLL IP Core Parameters - PLL Tab
UG-01155
2016.06.23
Altera Corporation
Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
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