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LVITD 2001-01
19
P/N Description LVITD - XXX X
LVC Buffered 10 Tap Delay
Molded Pac kage Series:
14-pin DIP:
LVITD
Total Delay i n nanoseconds (ns )
Lead Styl e: Blank = Thru-hol e
G = “Gull Wing” SMD
J = “J” Bend SMD
Exampl es: LVITD-30G = 30ns (3ns per t ap) 74LV C, 14-Pin G-S M D
LVITD-100 = 100ns (10ns per t ap) 74LV C, 14-Pin DIP
OPERATING SPECIFICATIONS
Supply V ol tage, V
CC
.......................................... 3.3 ± 0.3 VDC
Supply Current , I
CC
........................... 10 mA typ., 30 mA max.
Supply Current , I
CCL
: V
IN
= GND ......................... 22 mA max.
Supply Current , I
CCH
: V
IN
= V
CC
............................. 10 µA max.
Input Vol tage, V
I
..................................... 0 V min., 5.5 V max.
Logic “1” Input , V
IH
.................................................. 2.0 V min.
Logic “0” Input , V
IL
................................................. 0.8 V max.
Logic “1” Out, V
OH
: V
CC
= 3V & I
OH
= -24 mA............ 2.0 V m i n.
Logic “0” Out, V
OL
: V
CC
= 3V & I
OL
= 24 mA ......... 0.55 V max.
Input Capaci tance, C
I
............................................. 5 pF, typ.
Input Pul se Width, P
WI
.............................. 40% of Delay min.
Operating Temperature Range ......................... -40
O
to +85
O
C
Storage Temperature Range ........................ -65
O
to +150
O
C
TEST CONDITIONS
-- Low Voltage CM OS , LVC
V
CC
Supply Voltage ................................................ 3.30VDC
Input Pulse Voltage ................................................... 2.70V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurem ents made at 25
O
C
2. Delay Ti m es measured at 1.50V level of l eadi ng edge.
3. Rise Ti m es measured from 0.75V to 2.40V.
4. 50pf probe and fi xture load on output under test .
Dimensions in Inches (mm)
DIP DIP
G-SMD G-SMD
J-SMD
.300
(7.62)
.285
(7.24)
MAX.
.008 R
(0.20)
.365
(9.27)
MAX.
.010
(0.25)
TYP.
.120
(3.05)
MIN.
.250
(6.35)
MAX.
.020
(0.51)
.785
(19.94)
MAX.
.050
(1.27)
TYP.
.020
(0.51)
TYP.
.100
(2.54)
TYP.
.400 (10.16)
.430 (10.92)
.285
(7.24)
MAX.
.010
(0.25)
TYP.
.008 R
(0.20)
.030
(0.76)
TYP.
.250
(6.35)
MAX.
.015
(0.38)
TYP.
.785
(19.94)
MAX.
.050
(1.27)
TYP.
.020
(0.51)
TYP.
.100
(2.54)
TYP.
.330 (8.38)
MAX.
.020 R
(0.51)
.285
(7.24)
MAX.
.285 (7.24)
.260 (6.60)
.785
(19.94)
MAX.
.265
(6.73)
MAX.
.030
(0.76)
TYP.
.050
(1.27)
TYP.
.020
(0.51)
TYP.
.100
(2.54)
TYP.
J-SMD
LVITD
Ser ies
LVC Low Volta ge Logi c
10-Tap Delay Modules
LVC Logic
10 Tap P/N
Tap Delay Tolerances +/- 5% or 2ns (>15ns +/- 1.0ns)
Tap-to-Tap
(ns)
Tap 1 Tap 2 Tap 3 Tap 4 Tap 5 Tap 6 Tap 7 Tap 8 Tap 9 Total - Tap 10
LVITD-12
3 4 5 6 7 8 9 10 11 12 ± 2.5 1.0 ± 0.4
LVITD-21
3 5 7 9 11 13 15 17 19 21 ± 2.5 2.0 ± 0.6
LVITD-30
3 6 9 12 15 18 21 24 27 30 ± 2.5 3.0 ± 0.8
LVITD-50
5 10 15 20 25 30 35 40 45 50 ± 2.5 5.0 ± 1.8
LVITD-60
6 12 18 24 30 36 42 48 54 60 ± 3.0 6.0 ± 2.0
LVITD-75
7.5 15 22.5 30 37.5 45 52.5 60 67.5 75 ± 3.75 7.5 ± 2.0
LVITD-80
8 16 24 32 40 48 56 64 72 80 ± 4.0 8.0 ± 2.0
LVITD-100
10 20 30 40 50 60 70 80 90 100 ± 5.0 10.0 ± 2.0
LVITD-125
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 ± 6.25 12.5 ± 3.0
LVITD-150
15 30 45 60 75 90 105 120 135 150 ± 7.5 15.0 ± 3.0
Vcc
14
Tap1
13
Tap3
12
Tap5
11
Tap7
10
Tap9
9
Tap10
8
1
IN
N/C
3
Tap2
Tap4
5
Tap6
6
Tap8
7
GND
4
2
LVITD Schematic
Inputs accept voltages up to 5.5 V
74LVC type input can be driven from either 3.3V or 5V
devices. This allows delay module to serve as a
translator in a mixed 3.3V / 5V system environment.
Oper ati ng Te m p. -40
O
C to +85
O
C
Low Profile 14-Pin Package
Two Surface Mount Versions
For 5-Tap 8-Pin Versions see LVMDM Series
Elect ri cal Speci ficati ons at 25
O
C