15801 Chemical Lane, Hunti ngton Beach, CA 92649-1595
Phone: (714) 898-0960 • FAX: (714) 896-0971
www.rhombus -in d .c o m
•
email: sales@
rhombus-ind.com
Rhombus
Industries Inc.
For other values & Custom Desi gns, contact factory.
Specifications subject to change without notice.
FAMDM 9901
8-Pin SIP Package
FAST/TTL Logic Buffered
5 Equal Delay Taps
Operat ing Tempe rature
Rang e 0
O
C to +70
O
C
8-Pin DIP Versions: see FAMDM Series
14-Pin DIP Versions: see FAIDM Series
Low Vol tag e C M OS Ver sio ns
refe r to LVMDM / LVIDM Series
Elect ri cal Speci ficati ons at 25
O
C
** These part numbers do not have 5 equal taps. Tap-t o-Tap Del ays referenc e Tap 1.
FSIDM
Ser ies
FAST / TTL
Buffered 5-Tap Delay Modules
1
IN
5
67
Vcc
8
GND
23
4
Tap1
Tap2 Tap3 Tap4 Tap5
FSIDM
8-Pin SIP Schematic
OPERATING SPECIFICATIONS
V
CC
Supply Voltage ................................... 5.00 ± 0.25 VDC
I
CC
Supply Current .................................... 48 mA Maximum
Logic “1” Input : V
IH
........................ 2.00 V min., 5.50 V max.
I
IH
............................... 20
µ
A max. @ 2. 70V
Logic “0” Input : V
IL
..........................................
0.80 V max .
I
IL
............................................ -0.6 mA mA
V
OH
Logic “1” Voltage Out .................................. 2.40 V min.
V
OL
Logic “0” Voltage Out ............................... 0.50 V max.
P
WI
Input Pulse Width ............................. 40% of Delay min.
Operating Temperature Range ............................ 0
O
to 70
O
C
Storage Temperature Range ...................... -65
O
to +150
O
C
TEST CONDITIONS
-- FAST / TTL
V
CC
Supply Voltage................................................ 5.00VDC
Input Pulse Voltage ................................................... 3.20V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurem ents made at 25
O
C
2. Delay Ti m es measured at 1.50V level of leading edge.
3. Rise Ti m es measured from 0.75V to 2. 40V .
4. 10pf probe and fi xture load on output under test .
P/N Description FSIDM - XXX X
74F Buffered 5 Tap Del ay
Molded Pac kage Series:
8-pin SIP :
FSIDM
Total Delay i n nanoseconds (ns )
Lead Styl e: Blank = Thru-hol e
Exampl es: FSI DM -25 = 25ns (5ns per t ap)
74F,
8-Pin SI P
FSIDM-100 = 100ns (20ns per t ap)
74F, 8-Pin
SIP
.810
(20.57)
MAX.
.280
(7.11)
MAX.
.050
(1.27)
TYP.
.020
(0.51)
TYP.
.100
(2.54)
TYP.
.015
(0.38)
TYP.
MIN.
.120
(3.05)
.155 (3.94)
.145 (3.68)
.010
(0.25)
TYP.
.180
(4.57)
MAX.
Dimensions in Inches (mm)
FAST 5 Tap
8-Pin SIP P/N
Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns)
Tap-to-Tap
(ns)
Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5
FSIDM-7
3.0 4.0 5.0 6.0 7 ± 1.0 ∗∗ 1 ± 0.5
FSIDM-9
3.0 4.5 6.0 7.5 9 ± 1.0 ∗∗ 1.5 ± 0.5
FSIDM-11
3.0 5.0 7.0 9.0 11 ± 1.0 ∗∗ 2 ± 0.7
FSIDM-13
3.0 5.5 8.0 10.5 13 ± 1.5 ∗∗ 2.5 ± 1.0
FSIDM-15
3.0 6.0 9.0 12.0 15 ± 1.5 3 ± 1.0
FSIDM-20
4.0 8.0 12.0 16.0 20 ± 2.0 4 ± 1.5
FSIDM-25
5.0 10.0 15.0 20.0 25 ± 2.0 5 ± 2.0
FSIDM-30
6.0 12.0 18.0 24.0 30 ± 2.0 6 ± 2.0
FSIDM-35
7.0 14.0 21.0 28.0 35 ± 2.0 7 ± 2.0
FSIDM-40
8.0 16.0 24.0 32.0 40 ± 2.0 8 ± 2.0
FSIDM-50
10.0 20.0 30.0 40.0 50 ± 2.5 10 ± 2.0
FSIDM-60
12.0 24.0 36.0 48.0 60 ± 3.0 12 ± 2.0
FSIDM-75
15.0 30.0 45.0 60.0 75 ± 3.75 15 ± 2.5
FSIDM-100
20.0 40.0 60.0 80.0 100 ± 5.0 20 ± 3.0
FSIDM-125
25.0 50.0 75.0 100.0 125 ± 6.25 25 ± 3.0
FSIDM-150
30.0 60.0 90.0 120.0 150 ± 7.5 30 ± 3.0
FSIDM-200
40.0 80.0 120.0 160.0 200 ± 10.0 40 ± 4.0
FSIDM-250
50.0 100.0 150.0 200.0 250 ± 12.5 50 ± 5.0
FSIDM-350
70.0 140.0 210.0 280.0 350 ± 17.5 70 ± 5.0
FSIDM-500
100.0 200.0 300.0 400.0 500 ± 25.0 100 ± 10.0
FSIDM S eri es
Molded 8-Pin SIP Package