SPICE Device Model Si2308BDS
www.vishay.com
Vishay Siliconix
S14-1396-Rev. B, 14-Jul-14
1
Document Number: 68124
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
N-Channel 60 V (D-S) MOSFET
DESCRIPTION
The attached SPICE model describes the typical electrical
characteristics of the n-channel vertical DMOS. The
subcircuit model is extracted and optimized over the -55 °C
to +125 °C temperature ranges under the pulsed 0 V to 10 V
gate drive. The saturated output impedance is best fit at the
gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used
to model the gate charge characteristics while avoiding
convergence difficulties of the switched C
gd
model. All
model parameter values are optimized to provide a best fit
to the measured electrical data and are not intended as an
exact physical interpretation of the device.
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
•Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the -55 °C to +125 °C Temperature Range
• Model the Gate Charge
SU
BCIRCUIT MODEL SCHEMATIC
Note
• This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer
to the appropriate datasheet of the same number for guaranteed specification limits.
D
S
DBD
C
GS
M
1
G
3
R1
M
2
Gx
R
G
SPICE Device Model Si2308BDS
www.vishay.com
Vishay Siliconix
S14-1396-Rev. B, 14-Jul-14
2
Document Number: 68124
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
SPECIFICATIONS (T
J
= 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS
SIMULATED
DATA
MEASURED
DATA
UNIT
Static
Gate Threshold Voltage V
GS(th)
V
DS
= V
GS
, I
D
= 250 μA 1.9 - V
Drain-Source On-State Resistance
a
R
DS(on)
V
GS
= 10 V, I
D
= 1.9 A 0.126 0.130
Ω
V
GS
= 4.5 V, I
D
= 1.7 A 0.159 0.160
Forward Transconductance
a
g
fs
V
DS
= 15 V, I
D
= 1.9 A 4.2 5 S
Body Diode Voltage V
SD
I
S
= 1.5 A 0.78 0.80 V
Dynamic
b
Input Capacitance C
iss
V
DS
= 30 V, V
GS
= 0 V, f = 1 MHz
189 190
pF Output Capacitance C
oss
27 26
Reverse Transfer Capacitance C
rss
11 15
Total Gate Charge Q
g
V
DS
= 30 V, V
GS
= 10 V, I
D
= 1.9 A 3.6 4.5
nC
V
DS
= 30 V, V
GS
= 4.5 V, I
D
= 1.9 A
22.3
Gate-Source Charge Q
gs
0.80 0.80
Gate-Drain Charge Q
gd
1.1 1