Preliminary Technical Data
Mixed-Signal Dual-Core Control Processor
with ARM Cortex-M4/M0 and 16-bit ADCs
ADSP-CM411F/412F/413F/416F/417F/418F/419F
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SYSTEM FEATURES
Up to 240 MHz ARM Cortex-M4 with floating-point unit with
up to 160K Byte zero-wait-state ECC SRAM
Safety based dual independent- core concept
Up to 1M Byte high performance ECC FLASH that can execute
instructions at near SRAM speed
Highest precision, low latency 31-channel analog front end
100 MHz ARM Cortex-M0 supervisor core with 32K Byte zero
wait state ECC SRAM
Single 3.3 V power supply
Static memory controller (SMC) with asynchronous memory
interface that supports 8-bit and 16-bit memories
Heightened, 24-channel precision pulse PWM unit
Four 3
rd
or 4
th
order SINC filters for glueless connection of
sigma-delta modulators
Hardware based harmonic analysis engine (HAE)
Logic block array (LBA)
FFT signal spectrum monitor
MATH accelerator and FSAT blocks
Two CAN 2.0B interfaces and up to five UARTs
Two serial peripheral interface (SPI compatible) ports
Four encoder interfaces, two with frequency division
Package options:
176-lead (24 mm Γ 24 mm) LQFP_EP package
210-ball (15 mm Γ 15 mm) CSP_BGA package
ANALOG FRONT END
16-bit A/D converter with 24 multiplexed inputs, supporting
6-way simultaneous sampling and
6-channel conversion in 1.4ΞΌ seconds
Independent 14-bit, 7-channel auxiliary ADC with seven
inputs
ADC controllers (ADCC0/ADCC1) and DAC controller (DACC0)
12-bit D/A converter
Up to three 2.5 V precision voltage reference outputs
(For details, see ADC/DAC/Voltage Reference/Comparator
Specifications.)
Figure 1. ADSP-CM41xF Block Diagram
SYSTEM
CONTROL
BLOCKS
EVENT
CONTROL
SYSTEM
WATCHDOGS
JTAG, SWD,
CoreSightβ’ TRACE
PLL & POWER
MANAGEMENT
FAULT
MANAGEMENT
SECURIT
Y
Cortex-M0
PERIPHERALS
GPIO (59)
1Γ CAN
STATIC
MEMORY
CONTROLLER
(ASYNC I/F)
8Γ TIMER
24Γ PWM
1Γ TWI / I
2
C
4Γ UART
CRC
OCU
1x SPORT
1Γ SPI
UP TO
1M BYTE
FLASH
FLASH
32K BYTE
SRAM
SRAM
MAILBOX
SYSTEM
CONTROL
BLOCKS
EVENT
CONTROL
SYSTEM
WATCHDOGS
FAULT
MANAGEMENT
SECURIT
Y
SRAM
UP TO
160K BYTE
SRAM
Cortex-M4
MATH
CORDIC
PERIPHERALS
1Γ CAN
8Γ TIMER
1Γ UART
1Γ SPI
GPIO (14)
ADCC0
ADC0
AFE
H/W ENHANCEAFE
HAE
DACC0
DAC
ADCC1
ADC1/2
FFT
FOCP
LBA
SINC
FILTERS
SYSTEM FABRIC
SYSTEM FABRIC
LOCAL FABRIC
LOCAL FABRIC
FSAT
Rev. PrC | Page 2 of 120 | March 2018
ADSP-CM411F/412F/413F/416F/417F/418F/419F
Preliminary Technical Data
TABLE OF CONTENTS
General Description ................................................. 3
Analog Front End ................................................. 4
Dual-Core System Architecture .............................. 10
EmbeddedICE .................................................... 13
Processor Infrastructure ....................................... 13
Memory Architecture .......................................... 17
System Acceleration ............................................ 19
Security Features ................................................ 19
Security Features Disclaimer .................................. 19
Safety Features ................................................... 19
Processor Peripherals ........................................... 21
Clock and Power Management ............................... 24
System Debug .................................................... 26
Development Tools ............................................. 27
Additional Information ........................................ 27
Related Signal Chains .......................................... 27
ADSP-CM41xF Detailed Signal Descriptions ................ 28
176-Lead LQFP_EP Signal Descriptions ...................... 31
GPIO Multiplexing for 176-Lead LQFP_EP Package ...... 38
210-Ball CSP_BGA Signal Descriptions ....................... 41
GPIO Multiplexing for 210-Ball CSP_BGA Package ....... 47
ADSP-CM41xF Designer Quick Reference ................... 50
Specifications ........................................................ 60
Operating Conditions ........................................... 60
Electrical Characteristics ....................................... 63
ADC/DAC/Voltage Reference/Comparator
Specifications .................................................. 65
Flash Specifications .............................................. 71
Absolute Maximum Ratings ................................... 72
ESD Caution ...................................................... 72
Package Information ............................................ 72
Timing Specifications ........................................... 73
Processor Test Conditions ................................... 106
Output Drive Currents ....................................... 106
Environmental Conditions .................................. 108
ADSP-CM41xF 176-Lead LQFP_EP Lead
Assignments .................................................... 109
Numerical by Lead Number.................................. 109
Alphabetical by Pin Name ................................... 111
ADSP-CM41xF 210-Ball CSP_BGA Ball Assignments ... 113
Numerical by Ball Number .................................. 113
Alphabetical by Pin Name ................................... 115
Outline Dimensions .............................................. 118
Pre Release Products .......................................... 120
REVISION HISTORY
3/2018βRev. PrB to Rev. PrC
Changes to System Features ........................................ 1
Changes to ADSP-CM41xF Block Diagram .................... 1
Changes to Product Features ...................................... 3
Changes to PWM Pin Programmable Drive Strength ...... 16
Added Floating-Point Saturation (FSAT) Unit .............. 23
Changes to Internal Voltage Regulator Circuit .............. 26
Changes to ADSP-CM41xF Detailed Signal Descriptions . 28
Changes to ADSP-CM412F/CM413F/CM416F/CM417F 176-
Lead LQFP_EP Signal Descriptions ............................ 31
Changes to ADSP-CM411F/CM418F/CM419F 210-Ball
CSP_BGA Signal Descriptions .................................. 41
Changes to ADSP-CM41xF Designer Quick Reference .... 50
Changes to Operating Conditions .............................. 60
Changes to Clock Related Operating Conditions ........... 61
Changes to Electrical Characteristics ........................... 63
Changes to ADC Specifications βADC1, ADC2 ............. 65
Changes to DAC Specifications .................................. 67
Changes to Comparator Specifications ........................ 68
Added Table to Flash Specifications ............................ 71
Changes to Absolute Maximum Ratings ....................... 72
Changes to Clock and Reset Timing ............................ 73
Changes to Power-Up Reset Timing ............................ 74
Changes to Power-Down Timing ............................... 75
Changes to SPI PortβMaster Timing .......................... 87
Added Table 55, Figure 63, Figure 64, and Figure 65 to
PWMβ Heightened Precision (HP) Mode Timing ......... 99
Changes to Serial Wire Debug (SWD) Timing ............. 103
Changes to
Debug Interface (JTAG Emulation Port) Timing .......... 104
Added ADC Timing .............................................. 105
Added Figure 76, Capacitive Loading ........................ 107
Changes to Environmental Conditions ...................... 108