July, 2014 − Rev. 4

1 Publication Order Number:

NB7V52M/D

NB7V52M

1.8V / 2.5V Differential D

Flip-Flop w/ Reset and CML

Outputs

Multi−Level Inputs w/ Internal Termination

Description

The NB7V52M is a 10 GHz differential D flip−flop with a

differential asynchronous Reset. The differential D/D

, CLK/CLK and

R/R

inputs incorporate dual internal 50 W termination resistors and

will accept LVPECL, CML, LVDS logic levels.

When Clock transitions from logic Low to High, Data will be

transferred to the differential CML outputs. The differential Clock

inputs allow the NB7V52M to also be used as a negative edge

triggered device.

The 16 mA differential CML outputs provide matching internal

50 W termination and produce 400 mV output swings when externally

receiver terminated with a 50 W resistor to V

The NB7V52M is offered in a low profile 3 mm x 3 mm 16−pin

QFN package. The NB7V52M is a member of the GigaComm™

family of high performance clock products. Application notes,

models, and support documentation are available at

www.onsemi.com.

Features

• Maximum Input Clock Frequency > 10 GHz

• Maximum Input Data Rate > 10 Gb/s

• Random Clock Jitter < 0.8 ps RMS, Max

• 200 ps Typical Propagation Delay

• 35 ps Typical Rise and Fall Times

• Differential CML Outputs, 400 mV Peak−to−Peak, Typical

• Operating Range: V

= 1.71 V to 2.625 V with V

= 0 V

• Internal 50 W Input Termination Resistors

• QFN−16 Package, 3mm x 3mm

• −40°C to +85°C Ambient Operating Temperature

• These are Pb−Free Devices

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G = Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

MARKING

DIAGRAM*

QFN−16

MN SUFFIX

CASE 485G

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

NB7V

52M

ALYWG

Figure 1. Logic Diagram

RESET

D Flip−Flop

CLK

VTCLK

VTD

CLK

VTCLK

RVTR VTR

(Note: Microdot may be in either location)

NB7V52M

http://onsemi.com

VTCLK CLK CLK

VTCLK

VTR R R VTR

VCC

VEE

VTD

5678

16 15 14 13

NB7V52M

Exposed Pad (EP)

Figure 2. Pin Configuration (Top View)

Table 1. INPUT/OUTPUT SELECT TRUTH TABLE

R D CLK Q

H x x L

L L Z L

L H Z H

Z = LOW to HIGH Transition

x = Don’t care

Table 1. Pin Description

Pin Name I/O Description

1 VTD −

Internal 50 W Termination Pin for D

2 D LVPECL, CML,

LVDS Input

Noninverted Differential Data Input. (Note 1)

3 D LVPECL, CML,

LVDS Input

Inverted Differential Data Input. (Note 1)

4 VTD −

Internal 50 W Termination Pin for D

5 VTCLK −

Internal 50 W Termination Pin for CLK

6 CLK LVPECL, CML,

LVDS Input

Noninverted Differential Clock Input. (Note 1)

7 CLK LVPECL, CML,

LVDS Input

Inverted Differential Clock Input. (Note 1)

8 VTCLK −

Internal 50 W Termination Pin for CLK

9 VEE − Negative Supply Voltage. (Note 2)

10 Q CML Output Inverted Differential Output

11 Q CML Output Noninverted Differential Output

12 VCC − Positive Supply Voltage. (Note 2)

13 VTR −

Internal 50 W Termination Pin for R

14 R LVPECL, CML,

LVDS Input

Noninverted Asynchronous Differential Reset Input. (Note 1)

15 R LVPECL, CML,

LVDS Input

Inverted Asynchronous Differential Reset Input. (Note 1)

16 VTR −

Internal 50 W Termination Pin for R

− EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for

improved heat transfer out of package. The exposed pad must be attached to a heat−sinking

conduit. The pad is electrically connected to the die, and must be electrically and thermally con-

nected to VEE on the PC board.

1. In the differential configuration when the input termination pins (VTx, VTx) are connected to a common termination voltage or left open, and

if no signal is applied on CLK/CLK

input, then the device will be susceptible to self−oscillation.

2. All VCC and VEE pins must be externally connected to a power supply for proper operation.