VSC8664
Application Note
The VSC8664 PHY in Synchronous Ethernet Applications
The VSC8664 PHY in Synchronous Ethernet Applications
VPPD-02116 VSC8664 Application Note Revision 1.0
Contents
1 Revision History ............................................................................................................................. 1
1.1 Revision 1.0 ........................................................................................................................................ 1
2 Introduction ................................................................................................................................... 2
2.1 Audience ............................................................................................................................................. 2
2.2 References .......................................................................................................................................... 2
2.3 Terms and Abbreviations .................................................................................................................... 2
3 Synchronous Ethernet Overview ................................................................................................... 3
4 VSC8664-based Synchronous Ethernet Scheme ............................................................................ 4
4.1 Reference Clock (REFCLK) Input Requirements .................................................................................. 4
4.1.1 Frequency Value ...................................................................................................................................... 4
4.1.2 Frequency Tolerance ............................................................................................................................... 4
4.1.3 Jitter Tolerance ........................................................................................................................................ 4
4.2 Recovered Clock Outputs ................................................................................................................... 5
4.2.1 Enabling or Disabling Recovered Clock Output ....................................................................................... 5
4.2.2 Recovered Clock Frequency Selection ..................................................................................................... 5
4.2.3 Recovered Clock Jitter ............................................................................................................................ 5
4.2.4 Clock Source Selection ............................................................................................................................ 8
4.2.5 Recovered Clock Output Squelch ............................................................................................................ 9
4.3 Fast Link Failure Indication ................................................................................................................. 9
4.3.1 Fast Link Failure Indication Timing .......................................................................................................... 9
4.3.2 Enabling or Disabling Fast Link Failure Indication ................................................................................... 9
5 Configuring VSC8664 for Synchronous Ethernet ......................................................................... 10