Table of Contents
1. Functional Description............................
5
1.1 DSPLL.................................5
1.2 Si5381/82 LTE Frequency Configuration .....................7
1.3 Si5381/82 Configuration for JESD204B subclass 1 Clock Generation ...........8
1.4 DSPLL Loop Bandwidth ...........................9
1.4.1 Fastlock ...............................10
1.4.2 Holdover Exit Bandwidth .........................10
1.5 Dividers Overview .............................12
2. Modes of Operation ............................13
2.1 Reset and Initialization ...........................14
2.1.1 Updating Registers During Device Operation ..................15
2.1.2 NVM Programming ...........................16
2.2 Free Run Mode ..............................16
2.3 Lock Acquisition Mode ...........................16
2.4 Locked Mode ..............................16
2.5 Holdover Mode ..............................17
3. Clock Inputs (IN0, IN1, IN2, IN3/FB_IN) .....................20
3.1 Input Source Selection ...........................21
3.1.1 Manual Input Selection ..........................22
3.1.2 Automatic Input Switching .........................23
3.2 Types of Inputs ..............................23
3.2.1 Hitless Input Switching ..........................25
3.2.2 Ramped Input Switching .........................26
3.2.3 Glitchless Input Switching .........................26
3.2.4 Unused Inputs.............................26
3.3 Fault Monitoring .............................27
3.3.1 Input LOS (Loss-of-Signal) Detection .....................27
3.3.2 XAXB Reference Clock LOSXAXB (Loss-of-Signal) Detection ............28
3.3.3 Input OOF (Out-of-Frequency) Detection ....................29
3.3.4 DSPLL Loss-of-Lock (LOL) Detection .....................31
3.3.5 Device Status Monitoring .........................33
3.3.6 INTRb Interrupt Configuration .......................35
4. Output Clocks ..............................37
4.1 Output Crosspoint Switch ..........................37
4.1.1 Output R Divider Synchronization ......................38
4.2 Performance Guidelines for Outputs .......................39
4.2.1 Optimizing Output Phase Noise for Si5381/82 ..................40
4.3 Output Signal Format ............................40
4.4 Output Driver Supply Select .........................41
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