© 2017 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 05/12/17
TVS Diode Arrays (SPA
®
Diodes)
General Purpose ESD Protection - SP725 Series
Description
Features
• ESD Interface per HBM Standards
- IEC 61000-4-2, Direct Discharge .......... 8kV (Level 4)
- IEC 61000-4-2, Air Discharge ............... 15kV (Level 4)
- MIL-STD-3015.7 .................................................25kV
• Peak Current Capability
- IEC 61000-4-5 8/20 µs Peak Pulse Current ..... ± 14 A
- Single Transient Pulse, 100 µs Pulse Width ...... ± 8 A
• Designed to Provide Over-Voltage Protection
- Single-Ended Voltage Range to ........................ +30V
- Differential Voltage Range to ............................ ±15V
• Fast Switching .............................................. 2ns Risetime
• Low Input Leakages ..........................5 nA at 25 ºC Typical
• Low Input Capacitance ....................................5 pF Typical
• An Array of 4 SCR/Diode Pairs
• Operating Temperature Range..................-40 ºC to 105 ºC
Applications
The SP725 is an array of SCR/Diode bipolar structures for
ESD and overvoltage protection of sensitive input circuits.
The SP725 has 2 protection SCR/Diode device structures
per input. There are a total of 4 available inputs that can be
used to protect up to 4 external signal or bus lines. Over-
voltage protection is from the IN (Pins 1 - 4) to V+ or V-.
The SCR structures are designed for fast triggering at a
threshold of one +V
BE
diode threshold above V+ (Pin 5,6)
or one –V
BE
diode threshold below V- (Pin 7,8). From an
IN input, a clamp to V+ is activated if a transient pulse
causes the input to be increased to a voltage level greater
than one V
BE
above V+. A similar clamp to V- is activated if
a negative pulse, one V
BE
less than V-, is applied to an IN
input.
Refer to Fig 1 and Table 1 for further details. Refer to
Application Note AN9304 and AN9612 for further detail.
• Microprocessor/Logic
Input Protection
• Data Bus Protection
• Analog Device Input
Protection
• Voltage Clamp
Pinout
Functional Block Diagram
SP725
(SOIC)
1
2
3
4
8
7
6
5
In
In
In
V+
V+
V-
In
V-
Life Support Note:
Not Intended for Use in Life Support or Life Saving Applications
The products shown herein are not designed for use in life sustaining or life saving
applications unless otherwise expressly indicated.
RoHS
Pb
GREEN
SP725 Series 5pF 8kV Diode Array
Additional Information
Samples
Resources
© 2017 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 05/12/17
TVS Diode Arrays (SPA
®
Diodes)
General Purpose ESD Protection - SP725 Series
Absolute Maximum Ratings
Parameter Rating Units
Continuous Supply Voltage, (V+) - (V-) +35 V
Forward Peak Current, I
IN
to V
CC
, I
IN
to GND
(Refer to Figure 5)
± 8, 100 µs A
Peak Pulse Current, 8/20µs ± 14 A
ESD Ratings and Capability (Figure 1, Table 1)
Load Dump and Reverse Battery (Note 2)
Electrical Characteristics T
A
= -40
o
C to 105
o
C, V
IN
= 0.5V
CC
, Unless Otherwise Specified
Thermal Information
Parameter Rating Units
Thermal Resistance (Typical, Note 1) θ
JA
o
C/W
SOIC Package 170
o
C/W
Storage Temperature Range -65 to 150
o
C
Maximum Junction Temperature 150
o
C
Maximum Lead Temperature
(Soldering 20-40s) (SOIC - Lead Tips Only)
260
o
C
Parameter Symbol Test Conditions Min Typ Max Units
Operating Voltage Range,
V
SUPPLY
= [(V+) - (V-)]
V
SUPPLY
- 2 to 30 - V
Forward Voltage Drop
I
IN
= 2A (Peak Pulse)
IN to V- V
FWDL
- 2 - V
IN to V+ V
FWDH
- 2 - V
Input Leakage Current I
IN
-20 5 +20 nA
Quiescent Supply Current I
QUIESCENT
- 50 200 nA
Equivalent SCR ON Threshold (Note 3) - 1. 1 - V
Equivalent SCR ON Resistance V
FWD
/I
FWD
; (Note 3) - 0.5 - Ω
Input Capacitance C
IN
5 - pF
Input Switching Speed t
ON
- 2 - ns
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied.
Notes:
1. θ
JA
is measured with the component mounted on an evaluation PC board in free air
2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery V+ and V- pins are connected to the same supply
voltage source as the device or control line under protection, a current limiting resistor should be connected in series between the external supply and the SP725 supply pins to limit
reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- pins to ground are recommended.
3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance.” These characteristics are given here for thumb-rule information to determine peak
current and dissipation under EOS conditions.
(Application as an Input Clamp for Overvoltage, Greater than 1V
BE
Above V+ or less than -1V
BE
below V-)
Typical Application of the SP725