© Copyright 2017 Xilinx

Xilinx Answer 65444 – Xilinx PCI Express DMA Drivers and Software Guide 1

Xilinx Answer 65444

Xilinx PCI Express Windows DMA Drivers and Software Guide

Introduction

The Xilinx PCI Express DMA IP provides high-performance direct memory access (DMA) via PCI Express. The PCIe DMA

can be implemented in Xilinx 7 Series XT and UltraScale devices. This answer record provide drivers and software that

can be run on a PCI Express root port host PC to interact with the DMA endpoint IP via PCI Express. The drivers and

software provided with this answer record are designed for Windows 7 operating systems and can be used for lab testing

or as a reference for driver and software development. Through the use of the PCIe DMA IP and the associated drivers

and software you will be able to generate high-throughput PCIe memory transactions between a host PC and a Xilinx

FPGA.

PCIe DMA Driver for Windows Operating Systems

The following operating system is supported:

1. Download and unzip the ‘Xilinx_Answer_65444_Windows_Files_v2017_1.zip’ zip file supplied in this Answer

Record.

2. The Unzipped directory should have the following content:

3. Open the Device Manager (Control Panel -> System-> Device Manager)

4. Initially, the device will be displayed as a PCI Memory Controller device.

5. Right-Click on the device and select Update Driver Software and select the folder of the built XDMA driver

(located in sys/XDMA/).

6. If prompted about unverified driver publisher, select ‘Install this driver software anyway’ (see note below).

© Copyright 2017 Xilinx

Xilinx Answer 65444 – Xilinx PCI Express DMA Drivers and Software Guide 2

Sample Applications

Some basic applications that use the PCIe DMA kernel module driver have been included for reference. They can be

found in the bin/ directory of the supplied Answer Record zip file. They are further detailed in the sections below.

Xdma_test

This application is designed to run with the PCIe example design which implements a 4KByte BRAM buffer in the user

portion of the design. As such DMA transfers should be limited to 4 KByte transfers. For a 4 channel design this script

transfers 4096 bytes on each channel. The following functions are performed:

- Determines how many h2c and c2h channels are enabled in the PCIe DMA IP

- Determines if the PCIe DMA core is configured for memory mapped (AXI-MM) or streaming (AXI-ST) modes

This application opens the XDMA control device node via CreateFile() and executes ReadFile() to read status and control

registers of the XDMA IP core. These register values are then interpreted according to the register map in the IP

Documentation (PG195). The IP core configuration and status is then printed to console in human readable format.

Usage

xdma_info.exe

Xdma_rw

This application can be used to open any of the device nodes and perform read/write operations. Typically this is useful

for reading memory space of the control or user PCIe BARs. However it can also be used to perform aligned DMA

transfers via the h2c_* and c2h_* nodes, where the asterisk denotes the channel index (0-3). By default the host-side data

buffer that this application allocates is memory aligned to the PAGE_SIZE boundary (typically 4kB).

- OPTIONS :