Si5381/82 Evaluation Board User's Guide

The Si5381/82A-E-EB is used for evaluating the Ultra-Low Phase

Noise Quad/Dual PLL. The Si5381/82 employs fourth-generation

DSPLL technology to enable clock generation for LTE/ JESD204B

applications which require the highest level of jitter performance.

The Si5381/82A-E-EB has four independent input clocks and a to-

tal of 12 outputs with 4/2 PLLs. The Si5381/82A-E-EB also has

four independent input clocks and a total of 12 outputs with 2

PLLs. The Si5381/82A-E-EB can be easily controlled and config-

ured using Silicon Labs’ Clock Builder Pro™ (CBPro™) software

tool.

The device revision is distinguished by a white 1 inch x 0.187 inch label with the text

“Si5381/82A-E-EB” installed in the lower left hand corner of the board. (For ordering pur-

poses only, the terms “EB” and “EVB” refer to the board and the kit respectively. For the

purpose of this document, the terms are synonymous in context.)

EVB FEATURES

• Powered from USB port or external power

supply

• Onboard 54 MHz XO provides holdover

mode of operation on the Si5381/82

• CBPro GUI programmable VDDO supplies

allow each of the ten primary outputs to

have its own supply voltage selectable

from 3.3, 2.5, or 1.8 V

• CBPro GUI-controlled voltage, current,

and power measurements of VDD and all

VDDO supplies

• Status LEDs for power supplies and

control/status signals of Si5381/82

• SMA connectors for input clocks and

output clocks

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1. Si5381/82 Functional Block Diagram

Below is a functional block diagram of the Si5381/82A-E-EB. This EB can be connected to a PC via the main USB connector for pro-

gramming, control, and monitoring. See 2. Quick Start and Jumper Defaults or 6.1 Installing ClockBuilderPro (CBPro) Desktop Software

for more information.

Note: All Si5381/82 schematics, BOMs, User’s Guides, and software can be found online at the following link: http://www.silabs.com/

si538x-4x-evb

Input Clock 3

Si5381/82A

CLKOUT_0

CLKOUT_0B

Output

Termination

CLKOUT_1

CLKOUT_1B

Output

Termination

CLKOUT_2

CLKOUT_2B

Output

Termination

CLKOUT_3

CLKOUT_3B

Output

Termination

CLKOUT_4

CLKOUT_4B

Output

Termination

CLKOUT_5

CLKOUT_5B

Output

Termination

CLKOUT_6

CLKOUT_6B

Output

Termination

CLKOUT_7

CLKOUT_7B

Output

Termination

Input

Termination

Input

Termination

Input

Termination

CLKIN_0

CLKIN_0B

CLKIN_1

CLKIN_1B

CLKIN_2

CLKIN_2B

Power Supply

C8051F380

MCU

Peripherals

I2C/SPI Bus

VDDO_0

VDD_Core

VDD_3.3

VDDO_1

VDDO_2

VDDO_3

VDDO_4

VDDO_5

VDDO_6

VDDO_7

VDDO_0

VDD_Core

VDD_3.3

VDDO_1

VDDO_2

VDDO_3

VDDO_4

VDDO_5

VDDO_6

VDDO_7

USB +5V

Connector

Ext +5V

Connector

USB Aux +5V

Connector

I2C

+5V_USB

+5V_Aux

VDDMCU

Input Clock 0

{

Input Clock 1

{

Input Clock 2

{

}

Output Clock 0

}

Output Clock 1

}

Output Clock 2

}

Output Clock 3

}

Output Clock 4

}

Output Clock 5

}

Output Clock 6

}

Output Clock 7

Power only

VDDO_8

VDDO_9

VDDO_8

VDDO_9

CLKOUT_8

CLKOUT_8B

Output

Termination

}

Output Clock 8

CLKOUT_9

CLKOUT_9B

Output

Termination

}

Output Clock 9

Control/

Status

INTR

Alarm_Status

Input

Termination

CLKIN_3

CLKIN_3B

{

CLKOUT_0A

CLKOUT_0AB

Output

Termination

}

Output Clock 0A

CLKOUT_9A

CLKOUT_9AB

Output

Termination

}

Output Clock 9A

SPI

Conn

Ext Aux +5V

Connector

54 MHz

VDD_3.3V

Termination

Figure 1.1. Functional Block Diagram of Si5381/82A-E-EB

Si5381/82 Evaluation Board User's Guide

Si5381/82 Functional Block Diagram

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