1 Introduction

The Successive Approximation Register (SAR) Analog

Digital Converter (ADC) supports run-time hardware built in

self test to verify the operation of the ADC. The ADC self test

feature supports the testing of power supply integrity and

structural component integrity, e.g. capacitors, switches, and

comparators etc. The goal of this feature is to catch and flag

any run-time catastrophic errors leading to ADC functional

failure. The ADC self test includes two different self tests:

• Supply self test: Also referred to as algorithm S it is

used to verify the bandgap, supply (VDD_HV_ADV)

and reference (VDD_HV_ADR) voltages

• Capacitive self test: Also referred to as algorithm C it is

used to to check for opens or shorts in the capacitive

array

This document details supplemental information required to

operate the ADC self test feature. Two use case samples are

also given to help users understand how to program the ADC

self test feature.

ADC Self test feature

description

Freescale Semiconductor

Document Number: AN5015

Application Note

Rev 0, 09/2014

MPC574xP ADC Self Test

by: Arun Kumar, Sanjoy Dey, and Jamaal Fraser

Contents

1 Introduction................................................................1

2 ADC Self test feature description............. ................1

3 ADC Self test parameters..........................................3

4 Considerations for software based

comparison................................................................ 4

5 Sample code.............................................................. 6

For safety devices used in very critical applications it is important to check at regular intervals that the ADC is functioning

correctly. For this purpose the self testing feature has been incorporated inside the ADC. The self tests use analog watchdogs

to verify the results of the self test conversions. The upper and lower thresholds of these watchdogs are saved in the UTest

flash area. Before running the self test the user must copy these values from the UTest flash to the Self Test Analog

Watchdog Registers (ADC_STAWxR) or directly program their own values into the ADC_STAWxR registers. The ADC

also have watchdog timers that can be used to monitor the sequence of the self test algorithm and ensure that it completes

within a safe time period.

Two types of self testing algorithms have been implemented inside the ADC:

• Supply self test (algorithm S): It includes the conversion of the internal bandgap voltage, ADC supply voltage, and

ADC reference voltage. It includes a sequence of three test conversions (steps S0-S2) that should be executed

sequentially.

• Capacitive self test (algorithm C): It includes a sequence of 12 test conversions (steps) which set the capacitive

elements comprising the sampling DAC capacitors.

The ADC implements the following functions in order accomplish self testing:

• An additional test channel dedicated for self tests

• Signals to schedule self test algorithms using configuration registers

• Monitors the converted data using analog watchdog registers and flags the error at the output port of the ADC (for the

Fault Collection and Control Unit (FCCU)) in case any of the algorithms fail

See Figure 1 below.

Figure 1. ADC block diagram with self test feature

ADC Self test feature description

MPC574xP ADC Self Test, Rev 0, 09/2014

2 Freescale Semiconductor, Inc.