13.1.1 December 2013 Altera Corporation
RN-01080-13.1.1.0 Release Notes
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Altera Complete Design Suite Version
13.1 Update Release Notes
This document provides information about the Altera
®
Complete Design Suite
version 13.1 update 1.
You must either have previously installed the Quartus II software version 13.1 or must
install the Quartus II software version 13.1 before installing this update. Otherwise,
the update will not be installed correctly and the Quartus II software will not run
properly.
For information about the Quartus II software version 13.1, refer to the Quartus II
Software and Device Support Release Notes Version 13.1.
Issues Addressed in Update 1
The Altera Complete Design Suite version 13.1 update 1 addresses the following
software issues:
Device Support
■ Provides full compilation and programming support for the following Arria V
devices: 5ASXMB3E4F31I3 and 5ASXMB5E4F31I3.
■ Provides full compilation and programming support for the following Cyclone V
devices: 5CSEMA2, 5CSEBA2, 5CSXFC2, 5CSEMA4, 5CSEBA4, 5CSXFC4.
■ Fixes an issue in the Quartus II software version 13.1 related to minor
temperature-related routing resistance variances for Cyclone V devices and
reverts timing delays to match those in the Quartus II software version 13.0 SP1.
The impact to designs compiled with version 13.1 was small and is unlikely to
cause a silicon issue.
Nios II EDS
■ Corrects an issue that caused some Nios II EDS utilities to fail with no error output
or messages when run on a Windows PC. The affected utilities are:
sof2flash
,
elf2flash
,
elf2hex
and
bin2flash
.
Qsys
■ Adds UART1 pin location information for Arria V SoCs to the Peripherals Pin
Multiplexing tab in Qsys.
Issues Addressed in Update 1 Page 2
December 2013 Altera Corporation Altera Complete Design Suite Version 13.1 Update Release Notes
Quartus II Compilation Flows
■ Fixes missing Arria V GZ Programmable Power Technology Optimization settings
on the More Settings panel of the Fitter Settings dialog box in the Quartus II
software.
■ Fixes an internal error that was generated when a PLL clock is routed to external
IO pin with a
create_generated_clock
SDC assignment. The internal error
generated in previous versions of the Quartus II software was:
Internal Error: Sub-system: VPR20KMAIN, File:
/quartus/fitter/vpr20k/quartus_interface/qi_common/vpr_qi_tis_interface
.cpp, Line: 1161
■ Prevents an internal error in Advanced Single Event Upset (SEU) Detection, CvP
Update, and Partial Reconfiguration flows when Strictly Preserved logic is placed
into a single 1x1 Logic Lock region with no preserved routes leaving or entering
the region. The internal error prevented is:
Internal Error: Sub-system: MSF, File:
/quartus/db/msf/msf_masks_code.cpp, Line: 191 !routing.empty()
■ Fixes an issue in the Fitter where LVDS input buffers are powered by VCCPD, but
VCCIO was mistakenly assigned to LVDS input pins with differential OCT.
■ Fixes a problem with the register packer where register banks could be
accidentally merged within DSP inputs when the input to the Fitter came from
third party synthesis tools.
■ Fixes an issue in which the Quartus II Fitter fails to place one or more nodes,
including at least one dual-regional clock driver, generating an Error message
similar to
Error (175001): Could not place dual-regional clock driver
In previous versions of the Quartus II software, this error occurred after the Fitter
indicated that it had successfully placed all clocks in the design through messages
like
Info (11178): Promoted <x> clocks
... or
Info (11191): Automatically promoted <x> clocks
...
■ Removes incorrect error messages that can occur when using the Engineering
Change Order (ECO) Fitter flow.
■ Fixes an issue with VCCIO, VCCPD, and VCCN voltage rail settings in Stratix V
5SGXMBBR2H40I2L devices. Previous versions of the Quartus II software ignored
a Quartus II Settings File (.qsf) assignment of
set_global_assignment -name
STRATIX_DEVICE_IO_STANDARD "1.8 V"
and the I/O banks remained at 2.5 V.
Transceiver Toolkit
■ Fixes an issue in the Transceiver Toolkit that caused receiver-only autosweep to
always report a bit error rate of 1.