Design Guidelines for DisplayPort and HDMI Interfaces
2015-11-02
AN-745
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The design guidelines help you implement the DisplayPort and High-Definition Multimedia Interface
(HDMI) IP cores using Altera FPGA devices.
These guidelines facilitate board designs for the DisplayPort and HDMI IP video interfaces.
DisplayPort Design Guidelines
The DisplayPort IP core uses packetized data transmission and embeds the clock signal in the serial data
stream.
The DisplayPort interface consists of the following components:
• Main Link—Main Link transports video and/or audio streams and supports up to 4 lanes at 5.46
Gigabits per second (Gbps) per lane.
• AUX Channel—The DisplayPort source and sink devices use AUX Channel for link and device
management.
• Hot Plug Detect (HPD)—The DisplayPort sink device uses HPD to announce its presence or when it
requires the attention of the DisplayPort source device.
Main Link
Main Link of DisplayPort version 1.2 supports 1.62 Gbps, 2.7 Gbps, and 5.4 Gbps per lane, and provides a
link bandwidth scalable up to 21.6Gbps.
The Main Link consists of one, two, or four doubly terminated differential pairs or lanes with AC
coupling. The figure below depicts a Main Link lane with an FPGA transceiver PHY, a redriver, and AC-
coupling caps.
The FPGA transceiver PHY includes on-chip termination. The on-chip Vbias_TX (or Vbias_RX) voltage
is an internally generated common mode voltage. The redriver devices compensate for frequency-related
signal loss and cleans up jitter. An example of a DisplayPort 1.2 redriver device is TI SN75DP130 used in
the Bitec DisplayPort daughter card.
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Figure 1: Main Link Differential Pair with FPGA Transceiver PHY
This figure shows a standard implementation using redriver devices.
TX RX
50 Ω
V
bias
TX V
bias
RX
50 Ω
50 Ω
50 Ω
Source
Connector
Sink
Connector
Transceiver PHY Transmitter Transceiver PHY Receiver
Redriver Redriver
Altera recommends that you use DisplayPort redriver devices such as TI SN75DP130 to achieve reliable
signal integrity under various DisplayPort channel condition.
Table 1: DisplayPort Source and Sink Recommendation
The table provides guidelines on the usage of DisplayPort redriver devices.
Devices DisplayPort Source Redriver DisplayPort Sink Redriver
Arria 10 Recommended Required
Arria V GX/GT/GZ Recommended Required
Cyclone V GT Recommended Required
Stratix V GX/GT/GZ Recommended Required
For more information about the DisplayPort 1.2 redriver device, TI SN75DP130, refer to the
SN75DP130
DisplayPort 1:1 Redriver With Link Training datasheet.
DisplayPort Board Design Tips
When you design your DisplayPort system, consider the following board design tips.
• Use 135-MHz clock with minimal jitter for the DisplayPort transceiver PHY reference clock. Feed the
135-MHz clock directly through the REFCLK pin of the transceiver bank.
• Use no more than two vias per trace and avoid via stubs.
• Match the differential pair impedance to the impedance of the connector and cable assembly (100 ohm
±10%).
• Minimize inter-pair and intra-pair skews to meet the Main Link skew requirement.
• Avoid routing a differential pair over a gap in the underneath plane.
• Use standard high speed PCB design practices.
AUX Channel
The DisplayPort AUX channel is a half-duplex, bidirectional channel consisting of a differential pair.
2
DisplayPort Board Design Tips
AN-745
2015-11-02
Altera Corporation
Design Guidelines for DisplayPort and HDMI Interfaces
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