Serial Peripheral Interface Master in Altera MAX Series
2014.09.22
AN-485
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The serial peripheral interface (SPI) is a 4-wire, serial communication interface. SPI is an industry
standard protocol that is widely used in embedded systems for interfacing microprocessors and various
devices such as sensors, memory chips, shift registers, port expanders, display drivers, data converters,
printers, data storage devices, sensors, and multimedia cards.
This interface standard has several advantages:
• Low pin count and simple wiring
• Full-duplex communication for higher throughput (allowing faster communication compared to other
protocols such as I
2
C)
• No addressing; therefore, reduced overhead
Applications such as digital audio, digital signal processing, and telecommunication channels require
high-speed data streams. The low-power, high-speed Altera
®
MAX
®
II, MAX V and MAX 10 devices are
suitable for an SPI master, external to the host. This application note details the implementation of the SPI
master in MAX II, MAX V and MAX 10 devices. A microprocessor is used to control the master, which
you can use to select a slave device to read and write data to and from it.
Related Information
• Power Management in Portable Systems using Altera Devices
Provides more information about power management in portable systems using Altera devices
• MAX II Device Design Guidelines
Provides more information about MAX II device design guidelines
• Design Example for MAX II
Provides the MAX II design files for this application note (AN-485)
• Design Example for MAX 10
Provides the MAX 10 design files for this application note (AN-485)
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Using SPI Master in Altera Devices
Figure 1: Implementing an SPI Master using Supported Altera Devices
This figure shows the host interfacing ports and SPI slave interfacing ports. The host processor controls
the CPLD with the signals.
CS
Address [1:0]
Data Bus [7:0]
RD
WR
CLK
SCLK
MOSI
MISO
SS
SS
SS
Host
Processor
SPI Master
SPI
Slave
SPI
Slave
SPI
Slave
0
1
.
.
.
7
SPI Interface
The device communicates with the slave devices using:
• one data-out port (MOSI)
• one data-in port (MISO)
• clock (SCLK)
• slave select signal (SS)
Table 1: SPI Interface Pin Descriptions
This table lists the pin details for the interface.
Signal Purpose Description
MOSI master-out slave-in Outputs data from the master to the inputs of the slaves.
MISO master-in slave-out Inputs data from the master to the outputs of the slaves.
SCLK SPI clock Clock driven by the master to the slaves. Synchronizes the data bits.
SS slave select Select signal (active low) is driven by the master and sent to the
individual slaves. The SS signal selects the device (target slave) with
which the SPI master needs to communicate. You can connect up to
eight devices to the SPI master.
Note: SPI clock = host clock / (CLK DIV + 2).
Host Interface
The host selects the SPI master by holding the CS signal high. When CS is high, the address bus bits
determine to which SPI register the host is pointing. The host reads a particular register by keeping RD
high and writes into a register by keeping WR high. After completing the transmission of an SPI word, the
interrupt flag in the status register goes high. The host frequently monitors the status registers.
2
Using SPI Master in Altera Devices
AN-485
2014.09.22
Altera Corporation
Serial Peripheral Interface Master in Altera MAX Series
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