PT-5CSEMA6-1.4
Copyright © 2016 Alt era C orp.
Pin List U23 Page 1 of 15
Bank
Number
VREF PinName/Function (2) Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
U672 DQS for X8 DQS for X16
HMC Pi n Assignment for
DDR3/DDR2 (3)
HMC Pi n Assignment for
LPDDR2
HPS Pin Mux Sel ect 3
HPS Pin Mux Sel ect 2 HPS Pin Mux Sel ect 1 HPS Pin Mux Sel ect 0
3A TDO TDO Y9
3A nCSO DATA4 AA6
3A TMS TMS AC7
3A AS_DATA3 DATA3 AB6
3A TCK TCK AB5
3A AS_DATA2 DATA2 AC5
3A TDI TDI W10
3A AS_DATA1 DATA1 AC6
3A DCLK DCLK AA8
3A AS_DATA0,ASDO DATA0 AD7
3A VREFB3AN0 IO DATA6 DIFFIO_RX_B1n DIFFOUT_B1n Y8 DQ1B
3A VREFB3AN0 IO DATA5 DIFFIO_TX_B2n DIFFOUT_B2n Y4
3A VREFB3AN0 IO DATA8 DIFFIO_RX_B1p DIFFOUT_B1p W8 DQ1B
3A VREFB3AN0 IO DATA7 DIFFIO_TX_B2p DIFFOUT_B2p Y5 DQ1B
3A VREFB3AN0 IO DATA10 DIFFIO_RX_B3n DIFFOUT_B3n T8 DQSn1B
3A VREFB3AN0 IO DATA9 DIFFIO_TX_B4n DIFFOUT_B4n AB4 DQ1B
3A VREFB3AN0 IO DATA12 DIFFIO_RX_B3p DIFFOUT_B3p U9 DQS1B
3A VREFB3AN0 IO DATA11 DIFFIO_TX_B4p DIFFOUT_B4p AA4
3A VREFB3AN0 IO DATA14 DIFFIO_RX_B5n DIFFOUT_B5n V10 DQ1B
3A VREFB3AN0 IO DATA13 DIFFIO_TX_B6n DIFFOUT_B6n AD4 DQ1B
3A VREFB3AN0 IO CLKUSR DIFFIO_RX_B5p DIFFOUT_B5p U10 DQ1B
3A VREFB3AN0 IO DATA15 DIFFIO_TX_B6p DIFFOUT_B6p AC4 DQ1B
3A VREFB3AN0 IO PR_DONE DIFFIO_RX_B7n DIFFOUT_B7n AA11
3A VREFB3AN0 IO PR_READY DIFFIO_TX_B8n DIFFOUT_B8n AE6 DQ1B
3A VREFB3AN0 IO PR_ERROR DIFFIO_RX_B7p DIFFOUT_B7p Y11
3A VREFB3AN0 IO DIFFIO_TX_B8p DIFFOUT_B8p AD5 DQ1B
3B VREFB3BN0 IO DIFFIO_TX_B25n DIFFOUT_B25n AF4 GND GND
3B VREFB3BN0 IO DIFFIO_RX_B26n DIFFOUT_B26n AE9 DQ2B B_A_15
3B VREFB3BN0 IO DIFFIO_TX_B25p DIFFOUT_B25p AE4 DQ2B B_WE#
3B VREFB3BN0 IO DIFFIO_RX_B26p DIFFOUT_B26p AD10 DQ2B B_A_14
3B VREFB3BN0 IO DIFFIO_RX_B27n DIFFOUT_B27n U11 DQSn2B B_CS#_1 B_CS#_1
3B VREFB3BN0 IO DIFFIO_TX_B28n DIFFOUT_B28n AF8 DQ2B B_A_13
3B VREFB3BN0 IO DIFFIO_RX_B27p DIFFOUT_B27p T11 DQS2B B_CS#_0 B_CS#_0
3B VREFB3BN0 IO DIFFIO_TX_B28p DIFFOUT_B28p AE7 B_A_12
3B VREFB3BN0 IO DIFFIO_TX_B29n DIFFOUT_B29n AF9 DQ2B B_A_11
3B VREFB3BN0 IO DIFFIO_RX_B30n DIFFOUT_B30n AE11 DQ2B B_A_9 B_CA_9
3B VREFB3BN0 IO DIFFIO_TX_B29p DIFFOUT_B29p AE8 DQ2B B_A_10
3B VREFB3BN0 IO DIFFIO_RX_B30p DIFFOUT_B30p AD11 DQ2B B_A_8 B_CA_8
3B VREFB3BN0 IO CLK0n,FPLL_BL_FBn DIFFIO_RX_B31n DIFFOUT_B31n
W11
3B VREFB3BN0 IO DIFFIO_TX_B32n DIFFOUT_B32n AF6 DQ2B B_RAS#
3B VREFB3BN0 IO CLK0p,FPLL_BL_FBp DIFFIO_RX_B31p DIFFOUT_B31p V11
3B VREFB3BN0 IO DIFFIO_TX_B32p DIFFOUT_B32p AF5 DQ2B B_CAS#
3B VREFB3BN0 IO DIFFIO_TX_B33n DIFFOUT_B33n AG6 GND GND
3B VREFB3BN0 IO DIFFIO_RX_B34n DIFFOUT_B34n AF10 DQ3B B_BA_2
3B VREFB3BN0 IO DIFFIO_TX_B33p DIFFOUT_B33p AF7 DQ3B B_BA_0
3B VREFB3BN0 IO DIFFIO_RX_B34p DIFFOUT_B34p AF11 DQ3B B_BA_1
3B VREFB3BN0 IO DIFFIO_RX_B35n DIFFOUT_B35n T12 DQSn3B B_CK# B_CK#
3B VREFB3BN0 IO DIFFIO_TX_B36n DIFFOUT_B36n AH2 DQ3B B_A_7 B_CA_7
3B VREFB3BN0 IO DIFFIO_RX_B35p DIFFOUT_B35p T13 DQS3B B_CK B_CK
3B VREFB3BN0 IO DIFFIO_TX_B36p DIFFOUT_B36p AH3 B_A_6 B_CA_6
3B VREFB3BN0 IO FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn DIFFIO_TX_B37n DIFFOUT_B37n AH4 DQ3B B_A_3 B_CA_3
3B VREFB3BN0 IO DIFFIO_RX_B38n DIFFOUT_B38n AD12 DQ3B B_A_5 B_CA_5
3B VREFB3BN0 IO FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB DIFFIO_TX_B37p DIFFOUT_B37p AG5 DQ3B B_A_2 B_CA_2
3B VREFB3BN0 IO DIFFIO_RX_B38p DIFFOUT_B38p AE12 DQ3B B_A_4 B_CA_4
3B VREFB3BN0 IO CLK1n DIFFIO_RX_B39n
DIFFOUT_B39n W12
3B VREFB3BN0 IO DIFFIO_TX_B40n DIFFOUT_B40n AH5 DQ3B B_A_1 B_CA_1
3B VREFB3BN0 IO CLK1p DIFFIO_RX_B39p DIFFOUT_B39p V12
3B VREFB3BN0 IO DIFFIO_TX_B40p DIFFOUT_B40p AH6 DQ3B B_A_0 B_CA_0
4A VREFB4AN0 IO RZQ_0 DIFFIO_TX_B41n DIFFOUT_B41n AH7
4A VREFB4AN0 IO DIFFIO_RX_B42n DIFFOUT_B42n AF13 DQ4B B_DQ_0 B_DQ_0
4A VREFB4AN0 IO DIFFIO_TX_B41p DIFFOUT_B41p AG8 DQ4B B_DQ_2 B_DQ_2
4A VREFB4AN0 IO DIFFIO_RX_B42p DIFFOUT_B42p AG13 DQ4B B_DQ_1 B_DQ_1
4A VREFB4AN0 IO DIFFIO_RX_B43n DIFFOUT_B43n U13 DQSn4B B_DQS#_0 B_DQS#_0
4A VREFB4AN0 IO DIFFIO_TX_B44n DIFFOUT_B44n AH8 DQ4B B_DQ_3 B_DQ_3
4A VREFB4AN0 IO DIFFIO_RX_B43p DIFFOUT_B43p U14 DQS4B B_DQS_0 B_DQS_0
4A VREFB4AN0 IO DIFFIO_TX_B44p DIFFOUT_B44p AG9 B_ODT_0 B_ODT_0
4A VREFB4AN0 IO DIFFIO_TX_B45n DIFFOUT_B45n AH9 DQ4B B_ODT_1 B_ODT_1
4A VREFB4AN0 IO DIFFIO_RX_B46n DIFFOUT_B46n AE15 DQ4B B_DQ_4 B_DQ_4
4A VREFB4AN0 IO DIFFIO_TX_B45p DIFFOUT_B45p AG10 DQ4B B_DQ_6 B_DQ_6
4A VREFB4AN0 IO DIFFIO_RX_B46p DIFFOUT_B46p AF15 DQ4B B_DQ_5 B_DQ_5
4A VREFB4AN0
IO CLK2n DIFFIO_RX_B47n DIFFOUT_B47n AA13
4A VREFB4AN0 IO DIFFIO_TX_B48n DIFFOUT_B48n AH11 DQ4B B_DQ_7 B_DQ_7
4A VREFB4AN0 IO CLK2p DIFFIO_RX_B47p DIFFOUT_B47p Y13
4A VREFB4AN0 IO DIFFIO_TX_B48p DIFFOUT_B48p AG11 DQ4B B_DM_0 B_DM_0
4A VREFB4AN0 IO DIFFIO_RX_B50n DIFFOUT_B50n AG16 DQ5B DQ1B B_DQ_8 B_DQ_8
4A VREFB4AN0 IO DIFFIO_TX_B49p DIFFOUT_B49p AH12 DQ5B DQ1B B_DQ_10 B_DQ_10
4A VREFB4AN0 IO DIFFIO_RX_B50p DIFFOUT_B50p AF17 DQ5B DQ1B B_DQ_9 B_DQ_9
4A VREFB4AN0 IO DIFFIO_RX_B51n DIFFOUT_B51n V13 DQSn5B DQ1B B_DQS#_1 B_DQS#_1
4A VREFB4AN0 IO DIFFIO_TX_B52n DIFFOUT_B52n AH13 DQ5B DQ1B B_DQ_11 B_DQ_11
4A VREFB4AN0 IO DIFFIO_RX_B51p DIFFOUT_B51p W14 DQS5B DQ1B B_DQS_1 B_DQS_1
4A VREFB4AN0 IO DIFFIO_TX_B52p DIFFOUT_B52p AG14 B_CKE_1 B_CKE_1
4A VREFB4AN0 IO DIFFIO_TX_B53n DIFFOUT_B53n AH14 DQ5B DQ1B B_CKE_0 B_CKE_0
4A VREFB4AN0 IO DIFFIO_RX_B54n DIFFOUT_B54n AE17 DQ5B DQ1B B_DQ_12 B_DQ_12
4A VREFB4AN0 IO DIFFIO_TX_B53p DIFFOUT_B53p AG15 DQ5B DQ1B B_DQ_14 B_DQ_14
4A VREFB4AN0 IO DIFFIO_RX_B54p DIFFOUT_B54p AD17
DQ5B DQ1B B_DQ_13 B_DQ_13
4A VREFB4AN0 IO CLK3n DIFFIO_RX_B55n DIFFOUT_B55n AA15
4A VREFB4AN0 IO DIFFIO_TX_B56n DIFFOUT_B56n AH16 DQ5B DQ1B B_DQ_15 B_DQ_15
4A VREFB4AN0 IO CLK3p DIFFIO_RX_B55p DIFFOUT_B55p Y15
4A VREFB4AN0 IO DIFFIO_TX_B56p DIFFOUT_B56p AH17 DQ5B DQ1B B_DM_1 B_DM_1
4A VREFB4AN0 IO DIFFIO_RX_B58n DIFFOUT_B58n AD19 DQ6B DQ1B B_DQ_16 B_DQ_16
4A VREFB4AN0 IO DIFFIO_TX_B57p DIFFOUT_B57p AF18 DQ6B DQ1B B_DQ_18 B_DQ_18
4A VREFB4AN0 IO DIFFIO_RX_B58p DIFFOUT_B58p AE19 DQ6B DQ1B B_DQ_17 B_DQ_17
4A VREFB4AN0 IO DIFFIO_RX_B59n DIFFOUT_B59n AA18 DQSn6B DQSn1B B_DQS#_2 B_DQS#_2
4A VREFB4AN0 IO DIFFIO_TX_B60n DIFFOUT_B60n AH18 DQ6B DQ1B B_DQ_19 B_DQ_19
4A VREFB4AN0 IO DIFFIO_RX_B59p DIFFOUT_B59p AA19 DQS6B DQS1B B_DQS_2 B_DQS_2
4A VREFB4AN0 IO DIFFIO_TX_B60p DIFFOUT_B60p AG18 B_RESET# B_RESET#
4A VREFB4AN0 IO DIFFIO_TX_B61n DIFFOUT_B61n AH19 DQ6B DQ1B GND GND
4A VREFB4AN0 IO DIFFIO_RX_B62n DIFFOUT_B62n AD20 DQ6B DQ1B B_DQ_20 B_DQ_20
4A VREFB4AN0 IO DIFFIO_TX_B61p DIFFOUT_B61p AG19 DQ6B DQ1B
B_DQ_22 B_DQ_22
4A VREFB4AN0 IO DIFFIO_RX_B62p DIFFOUT_B62p AE20 DQ6B DQ1B B_DQ_21 B_DQ_21
4A VREFB4AN0 IO DIFFIO_TX_B64n DIFFOUT_B64n AG20 DQ6B DQ1B B_DQ_23 B_DQ_23
4A VREFB4AN0 IO DIFFIO_TX_B64p DIFFOUT_B64p AF20 DQ6B DQ1B B_DM_2 B_DM_2
4A VREFB4AN0 IO DIFFIO_RX_B66n DIFFOUT_B66n AF21 DQ7B DQ2B B_DQ_24 B_DQ_24
4A VREFB4AN0 IO DIFFIO_TX_B65p DIFFOUT_B65p AG21 DQ7B DQ2B B_DQ_26 B_DQ_26
4A VREFB4AN0 IO DIFFIO_RX_B66p DIFFOUT_B66p AF22 DQ7B DQ2B B_DQ_25 B_DQ_25
4A VREFB4AN0 IO DIFFIO_RX_B67n DIFFOUT_B67n AE22 DQSn7B DQ2B B_DQS#_3 B_DQS#_3
4A VREFB4AN0 IO DIFFIO_TX_B68n DIFFOUT_B68n AH21 DQ7B DQ2B B_DQ_27 B_DQ_27
4A VREFB4AN0 IO DIFFIO_RX_B67p DIFFOUT_B67p AD23 DQS7B DQ2B B_DQS_3 B_DQS_3
4A VREFB4AN0 IO DIFFIO_TX_B69n DIFFOUT_B69n AH22 DQ7B DQ2B GND GND
4A VREFB4AN0 IO DIFFIO_RX_B70n DIFFOUT_B70n AF23 DQ7B DQ2B B_DQ_28 B_DQ_28
4A VREFB4AN0 IO DIFFIO_TX_B69p DIFFOUT_B69p AH23 DQ7B DQ2B B_DQ_30 B_DQ_30
4A VREFB4AN0 IO DIFFIO_RX_B70p DIFFOUT_B70p AG23 DQ7B DQ2B B_DQ_29 B_DQ_29
4A VREFB4AN0 IO DIFFIO_TX_B72n DIFFOUT_B72n AH24 DQ7B DQ2B B_DQ_31 B_DQ_31
4A VREFB4AN0 IO DIFFIO_TX_B72p DIFFOUT_B72p AG24 DQ7B DQ2B B_DM_3 B_DM_3
4A VREFB4AN0 IO DIFFIO_RX_B74n DIFFOUT_B74n AE23 DQ8B DQ2B B_DQ_32 B_DQ_32
4A VREFB4AN0 IO DIFFIO_TX_B73p DIFFOUT_B73p AG26 DQ8B DQ2B B_DQ_34 B_DQ_34
4A VREFB4AN0 IO DIFFIO_RX_B74p DIFFOUT_B74p AE24 DQ8B DQ2B B_DQ_33 B_DQ_33
4A VREFB4AN0 IO DIFFIO_RX_B75n DIFFOUT_B75n AC23 DQSn8B DQSn2B B_DQS#_4 B_DQS#_4
4A VREFB4AN0 IO DIFFIO_TX_B76n DIFFOUT_B76n AH26 DQ8B DQ2B B_DQ_35 B_DQ_35
4A VREFB4AN0 IO DIFFIO_RX_B75p DIFFOUT_B75p AC22 DQS8B DQS2B B_DQS_4 B_DQS_4
4A VREFB4AN0 IO DIFFIO_TX_B77n DIFFOUT_B77n AH27 DQ8B DQ2B GND GND
4A VREFB4AN0 IO DIFFIO_RX_B78n DIFFOUT_B78n AG25 DQ8B DQ2B B_DQ_36 B_DQ_36
4A VREFB4AN0 IO DIFFIO_TX_B77p DIFFOUT_B77p AG28 DQ8B DQ2B B_DQ_38 B_DQ_38
4A VREFB4AN0 IO DIFFIO_RX_B78p DIFFOUT_B78p AF25 DQ8B DQ2B B_DQ_37 B_DQ_37
4A VREFB4AN0 IO DIFFIO_TX_B80n DIFFOUT_B80n AF28 DQ8B DQ2B B_DQ_39 B_DQ_39
Pin Infor mation f or t he Cyclone
®
V 5CSEMA6 Device
Version 1.4
Note (1)
PT-5CSEMA6-1.4
Copyright © 2016 Alt era C orp.
Pin List U23 Page 2 of 15
Bank
Number
VREF PinName/Function (2) Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
U672 DQS for X8 DQS for X16
HMC Pi n Assignment for
DDR3/DDR2 (3)
HMC Pi n Assignment for
LPDDR2
HPS Pin Mux Sel ect 3
HPS Pin Mux Sel ect 2 HPS Pin Mux Sel ect 1 HPS Pin Mux Sel ect 0
Pin Infor mation f or t he Cyclone
®
V 5CSEMA6 Device
Version 1.4
Note (1)
4A
VREFB4AN0 IO DIFFIO_TX_B80p DIFFOUT_B80p AF27 DQ8B DQ2B B_DM_4 B_DM_4
5A VREFB5AN0 IO RZQ_1 DIFFIO_TX_R1p DIFFOUT_R1p AF26 DQ1R
5A VREFB5AN0 IO INIT_DONE DIFFIO_RX_R2p DIFFOUT_R2p AA20
5A VREFB5AN0 IO PR_REQUEST DIFFIO_TX_R1n DIFFOUT_R1n AE26 DQ1R
5A VREFB5AN0 IO CRC_ERROR DIFFIO_RX_R2n DIFFOUT_R2n Y19
5A VREFB5AN0 IO nCEO DIFFIO_TX_R3p DIFFOUT_R3p AE25 DQ1R
5A VREFB5AN0 IO DIFFIO_RX_R4p DIFFOUT_R4p Y17 DQ1R
5A VREFB5AN0 IO CvP_CONFDONE DIFFIO_TX_R3n DIFFOUT_R3n AD26 DQ1R
5A VREFB5AN0 IO DIFFIO_RX_R4n DIFFOUT_R4n Y18 DQ1R
5A VREFB5AN0 IO DEV_OE DIFFIO_TX_R5p DIFFOUT_R5p AC24
5A VREFB5AN0 IO DIFFIO_RX_R6p DIFFOUT_R6p Y16 DQS1R
5A VREFB5AN0 IO DEV_CLRn DIFFIO_TX_R5n DIFFOUT_R5n AB23 DQ1R
5A VREFB5AN0 IO DIFFIO_RX_R6n DIFFOUT_R6n W15 DQSn1R
5A VREFB5AN0 IO DIFFIO_TX_R7p DIFFOUT_R7p AA24 DQ1R
5A VREFB5AN0 IO DIFFIO_RX_R8p DIFFOUT_R8p V16 DQ1R
5A VREFB5AN0 IO DIFFIO_TX_R7n DIFFOUT_R7n AA23
5A VREFB5AN0 IO DIFFIO_RX_R8n DIFFOUT_R8n V15 DQ1R
5B VREFB5BN0 IO CLK5p DIFFIO_RX_R21p DIFFOUT_R21p W21
5B VREFB5BN0 IO FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB DIFFIO_TX_R22p DIFFOUT_R22p AB26
5B VREFB5BN0 IO CLK5n
DIFFIO_RX_R21n DIFFOUT_R21n W20
5B VREFB5BN0 IO FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn DIFFIO_TX_R22n DIFFOUT_R22n AA26
5B VREFB5BN0 IO CLK4p,FPLL_BR_FBp DIFFIO_RX_R23p DIFFOUT_R23p Y24
5B VREFB5BN0 IO CLK4n,FPLL_BR_FBn DIFFIO_RX_R23n DIFFOUT_R23n W24
5B VREFB5BN0 IO RZQ_2 DIFFIO_TX_R24n DIFFOUT_R24n AB25
6B VREFB6BN0_HPS HPS_DDR AE28 HPS_DM_4 HPS_DM_4
6B VREFB6BN0_HPS HPS_DDR AD28 HPS_DQ_39 HPS_DQ_39
6B VREFB6BN0_HPS HPS_DDR V20 HPS_DQ_37 HPS_DQ_37
6B VREFB6BN0_HPS HPS_DDR AE27 HPS_DQ_38 HPS_DQ_38
6B VREFB6BN0_HPS HPS_DDR V19 HPS_DQ_36 HPS_DQ_36
6B VREFB6BN0_HPS HPS_DDR V18 HPS_DQS_4 HPS_DQS_4
6B VREFB6BN0_HPS HPS_GPI13 V24
6B VREFB6BN0_HPS HPS_DDR V17 HPS_DQS#_4 HPS_DQS#_4
6B VREFB6BN0_HPS HPS_DDR V25 HPS_DQ_35 HPS_DQ_35
6B VREFB6BN0_HPS HPS_DDR U25 HPS_DQ_33 HPS_DQ_33
6B VREFB6BN0_HPS HPS_DDR AC28 HPS_DQ_34 HPS_DQ_34
6B VREFB6BN0_HPS HPS_DDR T26 HPS_DQ_32 HPS_DQ_32
6B VREFB6BN0_HPS HPS_GPI12 AC27
6B VREFB6BN0_HPS HPS_GPI11 U16
6B VREFB6BN0_HPS HPS_DDR AB28 HPS_DM_3 HPS_DM_3
6B VREFB6BN0_HPS HPS_GPI10 U15
6B VREFB6BN0_HPS HPS_DDR AA27 HPS_DQ_31 HPS_DQ_31
6B VREFB6BN0_HPS HPS_DDR T24 HPS_DQ_29 HPS_DQ_29
6B VREFB6BN0_HPS HPS_DDR
Y27 HPS_DQ_30 HPS_DQ_30
6B VREFB6BN0_HPS HPS_DDR R24 HPS_DQ_28 HPS_DQ_28
6B VREFB6BN0_HPS VREFB6BN0_HPS T27
6B VREFB6BN0_HPS HPS_DDR U19 HPS_DQS_3 HPS_DQS_3
6B VREFB6BN0_HPS HPS_GPI9 Y26
6B VREFB6BN0_HPS HPS_DDR T20 HPS_DQS#_3 HPS_DQS#_3
6B VREFB6BN0_HPS HPS_DDR W26 HPS_DQ_27 HPS_DQ_27
6B VREFB6BN0_HPS HPS_DDR R25 HPS_DQ_25 HPS_DQ_25
6B VREFB6BN0_HPS HPS_DDR AA28 HPS_DQ_26 HPS_DQ_26
6B VREFB6BN0_HPS HPS_DDR R26 HPS_DQ_24 HPS_DQ_24
6B VREFB6BN0_HPS HPS_GPI8 Y28
6B VREFB6BN0_HPS HPS_GPI7 T16
6B VREFB6BN0_HPS HPS_DDR W28 HPS_DM_2 HPS_DM_2
6B VREFB6BN0_HPS HPS_GPI6 T17
6B VREFB6BN0_HPS HPS_DDR V27 HPS_DQ_23 HPS_DQ_23
6B VREFB6BN0_HPS HPS_DDR N27 HPS_DQ_21 HPS_DQ_21
6B VREFB6BN0_HPS HPS_DDR R27 HPS_DQ_22 HPS_DQ_22
6B VREFB6BN0_HPS HPS_DDR N26 HPS_DQ_20 HPS_DQ_20
6B VREFB6BN0_HPS HPS_GPI5 P26
6B VREFB6BN0_HPS HPS_DDR T19 HPS_DQS_2 HPS_DQS_2
6B VREFB6BN0_HPS HPS_DDR V28 HPS_RESET# HPS_RESET#
6B VREFB6BN0_HPS HPS_DDR T18 HPS_DQS#_2 HPS_DQS#_2
6B VREFB6BN0_HPS HPS_DDR U28 HPS_DQ_19 HPS_DQ_19
6B VREFB6BN0_HPS HPS_DDR N25 HPS_DQ_17 HPS_DQ_17
6B VREFB6BN0_HPS HPS_DDR T28 HPS_DQ_18
HPS_DQ_18
6B VREFB6BN0_HPS HPS_DDR N24 HPS_DQ_16 HPS_DQ_16
6B VREFB6BN0_HPS HPS_GPI4 R28
6A VREFB6AN0_HPS HPS_GPI3 R21
6A VREFB6AN0_HPS HPS_DDR P28 HPS_DM_1 HPS_DM_1
6A VREFB6AN0_HPS HPS_GPI2 R20
6A VREFB6AN0_HPS HPS_DDR N28 HPS_DQ_15 HPS_DQ_15
6A VREFB6AN0_HPS HPS_DDR M26 HPS_DQ_13 HPS_DQ_13
6A VREFB6AN0_HPS HPS_DDR M28 HPS_DQ_14 HPS_DQ_14
6A VREFB6AN0_HPS HPS_DDR M27 HPS_DQ_12 HPS_DQ_12
6A VREFB6AN0_HPS HPS_DDR L28 HPS_CKE_0 HPS_CKE_0
6A VREFB6AN0_HPS HPS_DDR R19 HPS_DQS_1 HPS_DQS_1
6A VREFB6AN0_HPS HPS_DDR K28 HPS_CKE_1 HPS_CKE_1
6A VREFB6AN0_HPS HPS_DDR R18 HPS_DQS#_1 HPS_DQS#_1
6A VREFB6AN0_HPS HPS_DDR J28 HPS_DQ_11 HPS_DQ_11
6A VREFB6AN0_HPS HPS_DDR L25 HPS_DQ_9 HPS_DQ_9
6A VREFB6AN0_HPS HPS_DDR J27 HPS_DQ_10 HPS_DQ_10
6A VREFB6AN0_HPS HPS_DDR K25 HPS_DQ_8 HPS_DQ_8
6A VREFB6AN0_HPS HPS_GPI1 K27
6A VREFB6AN0_HPS HPS_GPI0 M25
6A VREFB6AN0_HPS HPS_DDR G28 HPS_DM_0 HPS_DM_0
6A VREFB6AN0_HPS HPS_DDR F28 HPS_DQ_7 HPS_DQ_7
6A VREFB6AN0_HPS HPS_DDR K26 HPS_DQ_5 HPS_DQ_5
6A VREFB6AN0_HPS HPS_DDR G27 HPS_DQ_6 HPS_DQ_6
6A VREFB6AN0_HPS HPS_DDR J26 HPS_DQ_4
HPS_DQ_4
6A VREFB6AN0_HPS HPS_DDR G26 HPS_ODT_1 HPS_ODT_1
6A VREFB6AN0_HPS HPS_DDR R17 HPS_DQS_0 HPS_DQS_0
6A VREFB6AN0_HPS HPS_DDR D28 HPS_ODT_0 HPS_ODT_0
6A VREFB6AN0_HPS HPS_DDR R16 HPS_DQS#_0 HPS_DQS#_0
6A VREFB6AN0_HPS HPS_DDR D27 HPS_DQ_3 HPS_DQ_3
6A VREFB6AN0_HPS HPS_DDR J24 HPS_DQ_1 HPS_DQ_1
6A VREFB6AN0_HPS HPS_DDR E28 HPS_DQ_2 HPS_DQ_2
6A VREFB6AN0_HPS HPS_DDR J25 HPS_DQ_0 HPS_DQ_0
6A VREFB6AN0_HPS VREFB6AN0_HPS H28
6A VREFB6AN0_HPS HPS_DDR C28 HPS_A_0 HPS_CA_0
6A VREFB6AN0_HPS HPS_DDR B28 HPS_A_1 HPS_CA_1
6A VREFB6AN0_HPS HPS_DDR J21 HPS_A_4 HPS_CA_4
6A VREFB6AN0_HPS HPS_DDR E26 HPS_A_2 HPS_CA_2
6A VREFB6AN0_HPS HPS_DDR J20 HPS_A_5 HPS_CA_5
6A VREFB6AN0_HPS HPS_DDR D26 HPS_A_3 HPS_CA_3
6A VREFB6AN0_HPS HPS_DDR N21 HPS_CK HPS_CK
6A VREFB6AN0_HPS HPS_DDR C26 HPS_A_6 HPS_CA_6
6A VREFB6AN0_HPS HPS_DDR N20 HPS_CK# HPS_CK#
6A VREFB6AN0_HPS HPS_DDR B26 HPS_A_7 HPS_CA_7
6A VREFB6AN0_HPS HPS_DDR H25 HPS_BA_1
6A VREFB6AN0_HPS HPS_DDR A27 HPS_BA_0
6A VREFB6AN0_HPS HPS_DDR G25 HPS_BA_2
6A VREFB6AN0_HPS HPS_DDR A26 HPS_CAS#
6A
VREFB6AN0_HPS HPS_DDR A25 HPS_RAS#
6A VREFB6AN0_HPS HPS_DDR F26 HPS_A_8 HPS_CA_8
6A VREFB6AN0_HPS HPS_DDR A24 HPS_A_10
6A VREFB6AN0_HPS HPS_DDR F25 HPS_A_9 HPS_CA_9
6A VREFB6AN0_HPS HPS_DDR B24 HPS_A_11
6A VREFB6AN0_HPS HPS_DDR L21 HPS_CS#_0 HPS_CS#_0
6A VREFB6AN0_HPS HPS_DDR D24 HPS_A_12
6A VREFB6AN0_HPS HPS_DDR L20 HPS_CS#_1 HPS_CS#_1
6A VREFB6AN0_HPS HPS_DDR C24 HPS_A_13
6A VREFB6AN0_HPS HPS_DDR G23 HPS_A_14
6A VREFB6AN0_HPS HPS_DDR E25 HPS_WE#