NAND Flash Memory Interface with Altera MAX Series
2014.09.22
AN-500
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You can use an Altera
®
MAX
®
II, MAX V, or MAX 10 device to implement a NAND Flash Memory
Interface. You can use the design with both Samsung and AMD NAND Flash memories.
Related Information
• Design Example for MAX II
Provides the MAX II design files for this application note (AN 500)
• Design Example for MAX 10
Provides the MAX 10 design files for this application note (AN 500)
• MAX II Device Design Guidelines
Provides information about MAX II devices design guidelines
• Power Management in Portable Systems Using Altera Devices
Provides information about power management in portable systems using Altera devices
NAND Flash Interface Using Altera Devices
The commands from the system arrive at the inputs of the NAND Flash interface in coded form. Each
operation performed is coded in a different format and issues through the 3-bit wide control bus.
Enabling or disabling (in the case of ALE, CLE, SE, and WE) is done separately with the help of enable/
disable signal inputs. These commands are decoded correctly by the NAND Flash interface block (of the
supported Altera devices) and translated as output enabling or disabling signals, which ensures the
desired operation of the NAND Flash.
The actual operation performed by a NAND Flash is governed by the commands written into its
command register through the I/O bus. The address of the data that is read or written, together with the
data, are issued through the same bus.
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Figure 1: Interfacing Signals of the NAND Flash Device
This figure shows host interfacing signals and NAND Flash device interfacing signals. The signals
followed by a # are asserted when low.
READ/WRITE#
RESET
EN/DB#
CONTROL[2:0]
RY/BY#
I/O[7:0]
CLE
ALE
CE#
WE#
WP#
SE#
NAND Flash
Interface
NAND Flash
RE#
MAX II/MAX V/MAX 10
Microprocessor
Signals
Table 1: Interfacing Signals
This table lists the interfacing signals.
Signal Size Description
READ/WRITE# 1-bit Input from the microprocessor to distinguish between a write and
a read operation.
• READ/WRITE# 0: Write operation.
• READ/WRITE# 1: Read operation
RESET 1-bit Input from the microprocessor to reset the NAND Flash device.
CONTROL[2:0] 3-bit 3-bit control bus. The microprocessor sends 3 bits of information
to the NAND Flash interface (supported Altera devices) where it is
suitably decoded. The appropriate interfacing signals are enabled
or disabled depending on the condition of the EN/DB# input.
EN/DB# 1-bit Control bit used in conjunction with the control bits to perform
the required operation.
• EN/DB# 1: Enables the interfacing signal selected by the control
bits
• EN/DB# 0: Disables the interfacing signal selected by the control
bits.
I/O[7:0] 8-bit Bidirectional 8-bit multiplexed bus used to send data/command/
address to their respective registers in the NAND Flash device. The
data read from the NAND Flash device is also available on these
lines.
RY/BY# 1-bit Output from the NAND Flash device, indicating the status of the
device.
• RY/BY# 0 : Device is still busy performing an operation.
• RY/BY# 1 : Device is ready to accept the next command.
2
Signals
AN-500
2014.09.22
Altera Corporation
NAND Flash Memory Interface with Altera MAX Series
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