1. Introduction

Introduction

The MAX

II family of instant-on, non-volatile CPLDs is based on a 0.18-µm,

6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128

to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices

offer high I/O counts, fast performance, and reliable fitting versus other CPLD

architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and

enhanced in-system programmability (ISP), MAX II devices are designed to reduce

cost and power while providing programmable solutions for applications such as bus

bridging, I/O expansion, power-on reset (POR) and sequencing control, and device

configuration control.

Features

The MAX II CPLD has the following features:

■ Low-cost, low-power CPLD

■ Instant-on, non-volatile architecture

■ Standby current as low as 25 µA

■ Provides fast propagation delay and clock-to-output times

■ Provides four global clocks with two clocks available per logic array block (LAB)

■ UFM block up to 8 Kbits for non-volatile storage

■ MultiVolt core enabling external supply voltages to the device of either

3.3 V/2.5 V or 1.8 V

■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels

■ Bus-friendly architecture including programmable slew rate, drive strength,

bus-hold, and programmable pull-up resistors

■ Schmitt triggers enabling noise tolerant inputs (programmable per pin)

■ I/Os are fully compliant with the Peripheral Component Interconnect Special

Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V

operation at 66 MHz

■ Supports hot-socketing

■ Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry

compliant with IEEE Std. 1149.1-1990

■ ISP circuitry compliant with IEEE Std. 1532

MII51001-1.9

1–2 Chapter 1: Introduction

Features

MAX II Device Handbook © August 2009 Altera Corporation

Table 1–1 shows the MAX II family features.

f For more information about equivalent macrocells, refer to the MAX II Logic Element to

Macrocell Conversion Methodology white paper.

MAX II and MAX IIG devices are available in three speed grades: –3, –4, and –5, with

–3 being the fastest. Similarly, MAX IIZ devices are available in three speed grades: –6,

–7, and –8, with –6 being the fastest. These speed grades represent the overall relative

performance, not any specific timing parameter. For propagation delay timing

numbers within each speed grade and density, refer to the DC and Switching

Characteristics chapter in the MAX II Device Handbook.

Table 1–2 shows MAX II device speed-grade offerings.

Table 1–1. MAX II Family Features

Feature

EPM240

EPM240G

EPM570

EPM570G

EPM1270

EPM1270G

EPM2210

EPM2210G EPM240Z EPM570Z

LEs 240 570 1,270 2,210 240 570

Typical Equivalent Macrocells 192 440 980 1,700 192 440

Equivalent Macrocell Range 128 to 240 240 to 570 570 to 1,270 1,270 to 2,210 128 to 240 240 to 570

UFM Size (bits) 8,192 8,192 8,192 8,192 8,192 8,192

Maximum User I/O pins 80 160 212 272 80 160

PD1

(ns) (1) 4.7 5.4 6.2 7.0 7.5 9.0

CNT

(MHz) (2) 304 304 304 304 152 152

(ns) 1.7 1.2 1.2 1.2 2.3 2.2

(ns) 4.3 4.5 4.6 4.6 6.5 6.7

Notes to Ta bl e 1– 1 :

(1) t

PD1

represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic

implemented in a single LUT and LAB that is adjacent to the output pin.

(2) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster than this number.

Table 1–2. MAX II Speed Grades

Device

Speed Grade

–3 –4 –5 –6 –7 –8

EPM240

EPM240G

vvv———

EPM570

EPM570G

vvv———

EPM1270

EPM1270G

vvv———

EPM2210

EPM2210G

vvv———

EPM240Z — — — vvv

EPM570Z ��——vvv