Putting Altera MAX Series in Hibernation Mode Using
User Flash Memory
2016.01.14
AN-547
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The MAX
®
II, MAX V, and MAX 10 devices can be used in this example application.
You can completely power down the device into hibernation mode during an inactive period. The device
powers down automatically, and allows the system to power it up again when the system requires the
device to execute a task, while retaining the register data.
This example application shows the capability of the supported Altera device to store the register data into
the non-volatile user flash memory (UFM) before self-powering-down after an idle period. The device
also reads back the data from the UFM and reloads the registers for the device to resume operation shortly
after powering up.
Related Information
User Flash Memory (ALTUFM) Megafunction User Guide
Provides more information about the ALTUFM IP core.
Using User Flash Memory in MAX II Devices
User Flash Memory in MAX V Devices
MAX 10 User Flash Memory User Guide
Design Example for MAX II
Provides the MAX II design files for this application note (AN 547).
Design Example for MAX 10
Provides the MAX 10 design files for this application note (AN 547).
Design Example Description
The following design examples show the capability of the supported Altera device in a self-power-down
system. MAX II and MAX V devices are different from MAX 10 devices due to different flash memory
usage modes. The registers’ data is retained to ensure that the system’s operation is not affected by the
power-down. The example system consists of the design implemented in a MAX II, MAX V, or MAX 10
device as well as some external hardware circuitry. The hardware circuitry and the design in the device
work together to ensure the success of the self-power-down system.
In the example applications, a 4-bit binary up-counter is the user application module in which the
counter’s data must be retained when the supported Altera device is powered down after a predefined
period of inactivity. Upon power-up, the data is reloaded into the counter’s registers, so the count
operation resumes from the previous value.
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Supplying a trigger signal to the counter with a pushbutton (active low signal) increases the count value by
one. If the counter does not receive a trigger signal after a fixed duration, the design automatically stores
the count value into the UFM before triggering the external circuitry to power down the supported Altera
device.
For MAX II and MAX V devices, when the next trigger signal is received to increase the count, the device
automatically powers up. The design then reads back the data from the correct location in the UFM and
reloads the counter’s registers. The count value is incremented by one from the read-back data. For MAX
10 devices, pressing the trigger signal powers up the design and fetches the last value stored and puts the
value out on the LED display, but doesn't increment the value.
You can also reset the counter by pressing the reset button that clears the count value.
External Hardware Circuitry
An external circuitry is used to control the power supply to the supported Altera device, as well as the
input to the counter.
Figure 1: External Hardware Circuitry
The VCCINT/VCCIO power supplies are applicable for MAX II and MAX V devices only. The power
supplies for MAX 10 single supply devices are VCC_ONE, VCCA, and VCCIO. The power supplies for
MAX 10 dual supply devices are VCC, VCCD_PLL, VCCINT, VCCA, VCCA_ADC, and VCCIO.
Device
SW1
SW2
N1
10 kΩ
R1
1 kΩ
3.3V
R2
10 kΩ
PMOS
VCCINT/VCCIO
The VCCINT/VCCIO power supplies are for MAX II and MAX V devices only.
Power-Down-Ready
Count
Reset
Counter
Output
4
A P-channel MOSFET is used to control the power supply to the supported Altera device. If the gate of
the P-channel MOSFET is at low-voltage level, the transistor is turned on to allow current to flow through
from the power supply to the supported Altera device. If the transistor's gate is at a high-voltage level, the
transistor is turned off and the supported Altera device is in powered-down state.
The P-channel MOSFET can be steadily turned off with the 1-kΩ pull-up resistor R1. Besides, I/O pins of
the device do not drive out when the device is powered down.
2
External Hardware Circuitry
AN-547
2016.01.14
Altera Corporation
Putting Altera MAX Series in Hibernation Mode Using User Flash Memory
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