Altera Corporation 1
AN-469-1.1
Application Note 469
Stratix III Design Guidelines
Introduction
Stratix
®
III devices are engineered for high-speed core performance and
high-speed I/O with the best signal integrity in the industry, combined
with low-static and dynamic-power consumption. The devices also offer
increased logic density, so you can integrate more of your product to
reduce cost and board space.
It is important to follow Altera recommendations throughout the design
process for high-density, high-performance Stratix III designs. Planning
the FPGA and system early in the design process is crucial to your
success. This document provides an easy-to-use set of guidelines and a
list of factors to consider in Stratix III designs, but does not include all the
details about the product. It includes pointers to other documentation
where you can find detailed specifications, device feature descriptions,
and additional guidelines. The material covers the Stratix III device
architecture as well as aspects of the Quartus
®
II software and third-party
tools that you might use in your design.
The guidelines presented in this document will help you improve
productivity and avoid common design pitfalls. The document discusses
various stages of the design flow in the order that each stage is typically
performed, as shown in Table 1. You can use the “Design Checklist,” on
page 65 to help verify that you have followed each of the guidelines.
Table 1. Summary of Design Flow Stages and Guideline Topics (Part 1 of 2)
Stages of Design Flow Guideline Topics
“Device Selection,” on page 2
Device information, determining device density, package
offerings, speed grade, core voltage, migration, and
HardCopy
®
ASICs
“Planning for Device Configuration,” on page 6
Configuration scheme overview, configuration features,
Quartus II settings, optional pins
“Early System Planning,” on page 12
Planning: design specifications, IP selection, on-chip
debugging, early power estimation
“Board Design Considerations,” on page 18
Power-up, power pins, configuration pins, signal integrity,
board-level verification
“I/O and Clock Planning,” on page 27
Pin assignments, early pin planning, I/O features and
connections, clock and PLL selection, SSN
“Design and Compilation,” on page 42
Synthesis tools, coding styles and recommendations, planning
for hierarchical or team-based design, SOPC Builder
May 2008, version 1.1
Altera Corporation 2
Application Note 469: Stratix III Design Guidelines
f For complete details about the Stratix III device architecture, refer to the
Stratix III Literature page. For the latest known issues related to
Stratix III FPGAs, refer to the Stratix III Device Family Errata Sheet and the
Knowledge Database.
Device Selection
The first step in the Stratix III design process is to choose the device
family variant, device density, speed grade, package, and core voltage
that best suit your design needs. You should also consider whether you
want to target FPGA or ASIC migration devices. Before you begin
compiling a design in a third-party synthesis tool or the Quartus II
software, set the correct target device.
f For information about the features available in each device density,
including logic, memory blocks, multipliers, and phase-locked loops
(PLLs), as well the various package offerings and I/O pin counts, refer to
the Stratix III Device Family Overview chapter in volume 1 of the Stratix III
Device Handbook.
Logic, Memory, and Multiplier Density
The Stratix III logic family (L) offers balanced logic, memory, and
multipliers to address a wide range of applications, while the enhanced
family (E) offers more memory and multipliers per logic and is ideal for
wireless, medical imaging, and military applications. Choose the device
family variant with the best resource balance for your design
requirements.
Stratix III devices offer a range of densities that provide different amounts
of device logic resources, including memory, multipliers, and adaptive
logic module (ALM) logic cells. Different device densities may also offer
different numbers of features such as PLLs. Determining the required
logic density can be a challenging part of the design planning process.
Devices with more logic resources can implement larger and potentially
more complex designs, but generally have a higher cost. Smaller devices
have lower static power utilization. Select a device that meets your design
needs with some safety margin, in case you want to add more logic later
in the design cycle, or to upgrade or expand your design. You might also
“Timing Closure and Verification,” on page 50
Device utilization, timing constraints and analysis, area and
timing optimization, verification
“Power Analysis and Optimization,” on page 57
Analysis tools, optimization techniques, thermal management
options
Table 1. Summary of Design Flow Stages and Guideline Topics (Part 2 of 2)
Stages of Design Flow Guideline Topics