Altera Corporation 1

AN-380-1.2 Preliminary

Application Note 380

Test DDR or DDR2 SDRAM

Interfaces on Hardware

Using the Example Driver

Introduction

This application note describes how to test DDR or DDR2 SDRAM

interfaces on Altera

development boards using the Altera DDR or DDR2

SDRAM Controller MegaCore

function-generated example driver. The

example driver—a stand-alone synthesizable circuit—demonstrates the

DDR or DDR2 SDRAM interface. You can use these instructions to

quickly build a DDR or DDR2 SDRAM interface on one of the Altera

boards and see it working; or use the same principles to establish whether

the DDR or DDR2 SDRAM interface on your board is working as

expected, independently of any other circuit.

1 This application note describes a DDR2 SDRAM Controller

example driver, but is applicable to the Altera DDR SDRAM

Controller.

Figure 1 shows the example system block diagram.

Figure 1. Example System Block Diagram

DDR2 SDRAM

Controller

SignalTap II

Logic Analyzer

JTAG

Connector

DDR

DIMM

Altera Development Board

FPGA

Example

Driver

DDR SDRAM Interfac

Local Interface

June 2006 ver 1.2

2 Altera Corporation

Preliminary

Test DDR or DDR2 SDRAM Interfaces on Hardware

This application note details the following topics that help you build a

stand-alone synthesizable circuit that demonstrates the DDR2 SDRAM

interface:

■ “Overview” on page 2

■ “Set Up the Quartus II Project” on page 3

■ “Generate a DDR2 SDRAM Controller MegaCore Function” on

page 5

■ “Edit the PLL” on page 14

■ “Compile the Design” on page 17

■ “Select the Board Pin Outs” on page 16

■ “Set Up the SignalTap II Logic Analyzer” on page 18

■ “Program the Device” on page 23

Overview

A PC running the Quartus

II software downloads the device

programming file and monitors the activity on the DDR2 SDRAM

Controller local interface. The Quartus II SignalTap

II utility captures the

activity on the DDR2 SDRAM Controller local interface via the JTAG

connector.

The driver is a self-checking test generator for the DDR2 SDRAM

controller. The driver uses a state machine to write data patterns to a

range of column addresses, within a range of row addresses in all

memory banks. The driver then reads back the data from the same

locations, and checks that the data matches. The pnf (pass not fail) output

transitions low if any read data fails the comparison. There is also a

pnf_per_byte output, which shows the comparison on a per byte basis.

The test_complete output transitions high for a clock cycle at the end

of the write then read sequence. After this transition the test restarts from

the beginning and repeats indefinitely.

f For more information on pnf_per_byte, refer to “Appendix A:

Interpret the pnf_per_byte Output” on page 24.

The data patterns are generated with an 8-bit linear feedback shift register

(LFSR) per byte—each LFSR has a different initialization seed.

The application note requires the following hardware and software:

■ Cyclone™ II PCI Development Board, available in the PCI High-

Speed Development Kit, Cyclone II Edition

■ DDR2 SDRAM Controller MegaCore function

■ Quartus II software

1 The principles in this application note are the same for any

Altera development board.