
2 Altera Corporation
Using DDR and DDR2 SDRAM in Stratix III and Stratix IV Devices
Table 2 displays the maximum clock frequency for DDR and DDR2
SDRAM in Stratix IV devices.
DDR2 SDRAM Half –2 400
–3 333
–4
333 (5)
–4L (4)
200
Full –2 267
–3 233
–4 200
–4L (4)
167
Notes to Tab le 1 :
(1) Numbers are preliminary until characterization is final. The supported operating
frequencies are memory interface maximums for the device family. Your design's
actual achievable performance is based on design and system specific factors and
static timing analysis of the completed design.
(2) Applies to both DIMMs and components.
(3) Applies to both commercial and industrial devices.
(4) Performance is based on 0.9-V core voltage. At 1.1-V core voltage, the –4L speed
grade devices have the same performance as the –4 speed grade devices.
(5) Timing cannot be closed at the target speed in the Quartus II software version 8.0
but you can generate programming files. You can use these designs for
prototyping and testing, but you should not go to production until Altera releases
IP that can achieve these speeds.
Table 2. DDR and DDR2 SDRAM Maximum Clock Frequency Supported in
Stratix IV Devices (Part 1 of 2) Notes (1), (2), (3)
Type Speed Grade
f
MAX
(MHz)
DDR SDRAM –2 200
–3 200
–4 200
Table 1. DDR and DDR2 SDRAM Maximum Clock Frequency Supported in
Stratix III Devices (Part 2 of 2) Notes (1), (2), (3)
Type Rate Speed Grade
f
MAX
(MHz)