© February 2010 Altera Corporation AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices
AN 461: Design Guidelines for Implementing
QDRII+ and QDRII SRAM Interfaces in Stratix III
and Stratix IV Devices
QDRII+ and the QDRII SRAM devices are ideally suited for bandwidth– intensive
and low-latency applications such as controller buffer memory, look-up tables (LUTs),
and linked lists. QDRII+ and QDRII SRAM memory architecture features separate
read and write ports operating twice per clock cycle to deliver a total of four data
transfers per cycle.
Stratix
®
III and Stratix IV I/Os are specifically designed to support double-data rate
(DDR) external memory standards such as the QDRII+ and QDRII SRAM. Combined
with the new self-calibrating physical interface, the ALTMEMPHY megafunction,
Stratix III and Stratix IV devices deliver performance of up to 400 MHz or 1.6 Gbps on
top and bottom I/O banks.
For information about performance specifications, refer to the System Performance
Specification section of the External Memory Interface Handbook.
c The IP described in this document is scheduled for product obsolence and
discontinued support. Therefore, Altera
®
does not recommend use of this IP in new
designs. For more information about Altera’s current IP offering, refer to Altera’s
Intellectual Property website.
February 2010, v1.2
Page 2
AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices © February 2010 Altera Corporation
Figure 1 and Figure 2 show the Stratix III and the Stratix IV input, output, and
output-enable register paths for the QDRII+ and QDRII SRAM interface.
Figure 1. Stratix III and Stratix IV IOE Input Registers for QDRII+/QDRII SRAM Interface (Note 1)
Notes to Figure 1:
(1) You can bypass each register block in this path.
(2) This is the zero phase resynchronization clock (from read-leveling delay chain).
(3) The input clock comes either from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line.
(4) This input clock comes from the CQn logic block.
(5) This resynchronization clock comes either from the PLL or from the read-leveling delay chain.
(6) The I/O clock divider resides adjacent to the DQS logic block. In addition to the PLL and read-leveled resynchronization clock, the I/O clock divider
can also be fed by the DQS bus or CQn bus.
(7) The half-rate data and clock signals feed into a dual-port RAM in the FPGA core.
(8) You can dynamically change the dataoutbypass signal after configuration.
DFF
I
DFF
Input Reg A
Input Reg B
neg_reg_out
I
DQ
DQ
0
1
DQS
(3)
CQn
(4)
DQ
Input Reg C
I
DFF
DQ
DFF
DFF
DQ
DQ
DFF
DQ
DFF
DFF
D
Q
DQ
DFF
DQ
Resynchronization Clock
(resync_clk_2x)
(5)
Alignment & Synchronization Registers
Double Data Rate Input Registers
Half Data Rate Registers
To Core (rdata0)
(7)
To Core
(rdata1)
(7)
To Core (rdata2)
(7)
To Core
(rdata3)
(7)
to core
(7)
Half-Rate Resynchronization Clock (resync_clk_1x)
0
1
dataoutbypass
(8)
I/O Clock
Divider
(6)
(2)
DFF
D
Q
DFF
DQ
DFF
DQ
DFF
D
Q
DFF
DQ
DFF
DQ
DFF
DQ
DFF
DQ
DQSn
Differential
Input Buffer
0
1
0
.
.
7