© June 2008 Altera Corporation AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices
AN 461: Design Guidelines for Implementing
QDRII+ and QDRII SRAM Interfaces in Stratix III
and Stratix IV Devices
Introduction
QDRII+ and the QDRII SRAM devices are ideally suited for bandwidth– intensive
and low-latency applications such as controller buffer memory, look-up tables (LUTs),
and linked lists. QDRII+ and QDRII SRAM memory architecture features separate
read and write ports operating twice per clock cycle to deliver a total of four data
transfers per cycle.
Stratix
®
III and Stratix IV I/Os are specifically designed to support double-data rate
(DDR) external memory standards such as the QDRII+ and QDRII SRAM. Combined
with the new self-calibrating physical interface, the ALTMEMPHY megafunction,
Stratix III and Stratix IV devices deliver performance of up to 400 MHz or 1.6 Gbps on
top and bottom I/O banks. Table 1 lists the maximum clock rate support for Stratix III
devices interfacing with QDRII+ and QDRII SRAM devices.
Table 1. Stratix III Maximum Clock Rate Support for External Memory Interfaces with Half-Rate PHY (Note 1), (2)
Memory
Standards
-2 Speed
Grade
-3 Speed
Grade
-4 Speed
Grade -4L Speed Grade
Unit
VCCL = 1.1 V VCCL = 1.1 V VCCL = 1.1 V VCCL = 1.1 V VCCL = 0.9 V
Column I/O/ Row I/O Banks
(4)
Hybrid mode (4)
Column I/O/ Row I/O Banks
(4)
Hybrid mode (4)
Column I/O/ Row I/O Banks
(4)
Hybrid mode (4)
Column I/O/ Row I/O Banks
(4)
Hybrid mode (4)
Column I/O/ Row I/O Banks
(4)
Hybrid mode (4)
QDRII+ SRAM (2.5 clock
cycle latency only) (3)
400 300 350 250 300 250 300 250 — — MHz
QDRII SRAM (1.5V or
1.8V)(3)
350 300 300 250 300 250 300 250 167 167 MHz
Notes to Table 1:
(1) Numbers are preliminary until characterization is final. The supported operating frequencies listed here are memory interface maximums for
the FPGA device family. Your design’s actual achievable performance is based on design and system-specific factors, as well as static timing
analysis of the completed design.
(2) The maximum clock rate support for the external memory interfaces with the half-rate PHY stated in the table applies to both commercial and
industrial grade.
(3) Stratix III devices in the 780- and 1152-pin packages support
×36 QDRII+/QDRII SRAM at a lower maximum frequency as detailed in Table 3.
(4) The Column I/Os refer to Top and Bottom I/Os. The Row I/Os refer to Left and Right I/Os. Hybrid mode refers to DQ/DQS groups wrapping over
Column I/Os and Row I/Os of the device.
July 2008, v1.1
Page 2 Introduction
AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices © June 2008 Altera Corporation
Table 2 lists the maximum clock rate support for the Stratix IV devices interfacing
with QDRII+ and QDRII SRAM devices.
Table 2. Stratix IV Maximum Clock Rate Support for External Memory Interfaces with Half-Rate PHY (Note 1)
Memory Standards
All Stratix IV E Devices and Stratix IV GX
devices with 1152-pin (with 24
transceivers), 1517-pin, and 1932-pin
packages
Stratix IV GX devices with
780-pin and 1152- pin (with
16 transceivers) packages
Unit
Top/Bottom I/O Banks
Left/Right
I/O Bank (2) All I/O Banks (2)
–2
Speed
Grade
–3
Speed
Grade
–4
Speed
Grade
–2, –3, –4
Speed
Grade –2,–3,–4 Speed Grade
QDRII+ SRAM (2.5 clock cycle
latency only) (3)
400 350 300 300 300 MHz
QDRII SRAM (1.5-V & 1.8-V
HSTL) (3)
350 300 300 300 300 MHz
Notes to Table 2:
(1) Numbers are preliminary until characterization is final. The supported operating frequencies listed here are the memory interface maximum
for the FPGA device family. Your design’s actual achievable performance is based on the design and system-specific factors, as well as
static-timing analysis of the completed design.
(2) The left and the right I/O banks do not support 1.5 V HSTL and SSTL Class II I/O standards.
(3) Stratix IV devices in the 780- and 1152-pin packages support
×36 QDRII+/QDRII SRAM at a lower maximum frequency as detailed in Table 4.