Freescale Semicondu ctor

Application Note

NOR-based Flash memory devices have traditionally been

used for non- volatile s torage for a boo tloader. The advantages

of this type of memory include support for execute-in-place

code, random access to memory, and zero error rate.

Because of their higher density and lower cost per byte, NAND

Flash te chnologies are becoming more common.

Unfortunately, the technology comes with a major

disadvantage, which is the early failure of bits during memory

writes. After some number of erase cycles, some bits lose the

ability to be programmed to a zero state. Block-based error

correction solves this problem, but i t prevents random memory

accesses for execute-in-place code without a specialized

NAND Flash memory controller.

The local bus controller in the PowerQUI CC™ MPC8313E

processor is enhanced with a s pecialized NAND Fl ash contr ol

machine (FCM) to provide hardware support for smal l- and

large-page NAND Flash-based memories, including the ability

to boot from NAND Flash memory.

This application note provides a brief ove rview of the FC M

operation and describes the implementation of a bootloader

using u-boot [1] for the MPC8313 device with a small-pa ge

NAND device (Samsung K9F5608U0D and Micron

MT29F2G08AACWP).

Contents

1 MPC8313 Flash Control Machine . . . . . . . . . . . . . . . . 2

1.1Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3Error Checking and Correction. . . . . . . . . . . . . . . . 4

1.4NAND Boot Sequencer . . . . . . . . . . . . . . . . . . . . . 5

2 U-boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1Stage 0 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.2Board Configuration Settings for NAND boot. . . . 6

2.3u-boot files for NAND Boot . . . . . . . . . . . . . . . . . . 8

2.4NAND u-boot Execution Sequence . . . . . . . . . . . . 8

3 Building and Loading NAND u-boot . . . . . . . . . . . . . .9

4 NAND Auto Boot Settings on RDB Board . . . . . . . .10

5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Appendix ANAND u-boot Macros. . . . . . . . . . . . . . . . . . . 11

Appendix BNAND u-boot Code. . . . . . . . . . . . . . . . . . . . . 12

Using U-boot to Boot From a NAND

Flash Memory Device for MPC8313E

by Nick Spence

Network Computing Syste ms Grou p,

Freescale Semiconductor, Inc.

Document Number: AN3201

Rev. 0, 06/2007

Using U-boot to Boot From a NAND Flash Memory De vice for MPC8313E, Rev. 0

2 Freescale Semiconductor

MPC8313 Flash Control Machine

1 MPC8313 Flash Control Machine

The FCM in the enhanced local bus controller (eLBC) is dedicated to supporting NAND Flash memory

devices. It supports 8-bit small-page (512 byte) and 2048-byte large-page devices, offloading all NAND

memory access and optiona lly error checki ng/cor rec tion (ECC ) from the main processor to the FCM,

including the hardware interfacing.

The FCM works in conjunction w ith the boot sequencer to e nable the NAND Fla sh memory to store the

hardware reset configuration word (HRCW) and stage 0 bootloader in the first 4 Kbytes of the first good

block of memory in the NAND Flash memory device. Only the main features of the FCM are described

here. For a complete description, refer to the MPC8313E reference manual [2].

1.1 Registers

The FCM is controlled and monitored by a set of new registers in the eLBC block, as well as some existing

eLBC regist er s. The se regist er s are listed in Table 1 and Table 2, re s pectively.

Table 1. New eLBC Registers Used by the FCM

Flash mode register (FMR) Sets the mode of FCM operation, including the command wait

time-o ut, boot mode, ECC mode, and add ress length.

0x50E0

Flash instruction register (FIR) Contains a sequence of up to eight FCM instructions. 0x50E4

Flash command register (FCR) Contains Flash memory command opcode bytes. It can hold up to a

maximum of four such commands.

0x50E8

Flash b lock address r egister (FBAR) Contains the block index . 0x50EC

Flash page address register (FPAR) Contains the page and column indices. 0x50F0

Flas h byte count regi ster (FBCR) Contain s the count of bytes written i nto or read from the Flas h memory

device. When this register contains a val ue of zero, the entire page is

read fro m the Fla sh me mo ry dev ice. The hardware ECC can be

generat ed/chec ked o nly when the entir e page i s tr ansf erred by se tting

the byte count to 0.

0x50F4

Table 2. Existing eLBC Registers Reused by the FCM

Special operation i nitiation register

(LSOR)

Used by software to start a NAND Flash access. 0x5090

Transfer error statu s regi ster (LTESR) Indic ates the cause of an error or event. 0x50B0

T ransfer error check dis able register

(LTEDR)

Allows event or error checks to be disabled 0x50B4

Transfer interrupt enable regis ter

(LTEIR)

Selects events or errors that can generate an eLBC inte rr upt. 0x 50B8

Transfer error attributes register

(LTEATR)

Provid es infor mation about the er ror t ransact ion and m ust be cl eared

before the next event or error can be captured

0x50BC