Engineer-to-Enginee r Not e EE-398

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ADSP-CM41x Board Design Guide lines for Optimal ADC Perfor manc e

Contributed by Leo Mathew Rev 1 – March 30, 2017

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Introduction

ADSP-CM41xF are a family of dual core mixed-signal control processors based on the ARM

Cortex-M4™

core with floating point unit operating at frequencies up to 240 MHz, and the ARM

Cortex-M0

processor

core operating a t frequencies up to 100 MHz consisting of two 16-bit SAR-type ADCs, one 14-bit ADC and

one 12-bit DAC, along with the associated analog subsystem and a rich s et of per ip heral s an d a ccelerator s.

By integrating a rich set of industry-leading s yst em peripherals and memory, the ADSP-CM41xF mixed-

signal control processors are the platform of choice for next-generation applications that require RISC

programmability and leading-edge signal processing in one integrated package.

When designing ADSP-CM41xF-based systems for optimal ADC performance, mixed-signal design

aspects such as selection, placeme nt, and partitioning of analog and digital components must be considered.

As the processor, its peripherals, I/Os, and related digital circuits operate at higher clock rates, a significant

amount of noise and radiation may degrade the ADC performance. Sustaining ADC performance in a hostile

digital environment depends on good design techniques such as proper decoupling, signal routing and

grounding. Design problems can result in inaccurate ADC readings, excessive electromagnetic interference

(EMI), and unwanted system behavior. Careful management of the board design process ensures better

system control and reliability required for precision measurement and control systems. It also significantly

reduces development time. This document provides some guidelines for consideration while designing

ADSP-CM41xF-based boards with a specific focus on how to achieve the best performance from the

processor’s ADCs.

ADC Front-End Circuit Design

The analog subsystem of the ADSP-CM41xF processor contains two 16-bit, high-speed, low-power

Successive Approximation Register (SAR)-type ADCs. SAR ADCs offer high resolution, excellent

accuracy, and low power consumpti on. ADC1 and ADC2 ea ch have a m ax imum of 12 multiplexed analog

input channels, while ADC0 has 7 multiplexed analog input channels. The board design guidelines given

here mostly focus on the primary ADCs- ADC1 and ADC2 while most of the best practices can be utilized

for ADC0 as well.

To get t he best perfo rma nce f rom S AR-typ e A DC s , designers should first focus on the desi gn of the ADC

front end, which interfaces the analog input signal to the ADC input channel. It consists of two parts: the

driving operational amplifier (op-amp) and the RC filter shown in Figure 1.

ADSP-CM41x Board Design Guidelines for Optimal ADC Performance (EE-398) Page 2 of 15

Figure 1. SAR ADC Front End Circuit Design

The amplifier conditions the input signal and a cts as a low-impedance buffer between the signal source and

the ADC inpu t. The RC filte r limits th e a mount o f out-of-band noise arriving at the A DC input and helps to

attenuate the kick from the switched capac itors in the ADC’s input. The RC network also helps to relax the

driving op-amp requirements.

Apart from the analog front end circuit, a signal conditioning circuit may also be required, depending upon

the range of the input signal. The ADSP-CM41xF ADC accepts analog signals in the range of 0-3V, which

can be achieved by conditioning the analog input signal.

RC Filter Design

The input signal bandwidth determines the low-noise needed over that frequency spectrum to get a good

Signal-to-Noise Ratio (SNR). The RC filter network limits the bandwidth of the input signal and reduces

the amount of noise fed to the ADC by the amplifier and other upstream circuitry. However, too much band-

limiting will increase the settling time and distort the input signal.

To select a suitable RC filter, the RC bandwidth for the AD C channe l must be calc ulated, which is described

in the Front-End A mplifier and RC Filter Design for a Prec ision SAR Analog-to-Digital Conv erter article

[2]

Using the theory described in this article, consider the case where the maximum input sine wave frequency

to the ADC is 5 kHz, and the maximum input voltage is 3V (V

PEAK

= 1 .5V). The values of the external R-

C components, R

EXT

and C

EXT

, can be calculated using the following specifications from the data sheet

[1]

•

ADC Conversion Time (TCONV) = 340ns

•

ADC Acquisition Time (TACQ) = 280ns

The one LSB voltage value for a 16-bit ADC with 3V VREF is 45.77µV; therefore, 1/4th the LSB voltage

(V1/4LSB, required to settle for best SINAD) is 11.44µV.

The voltage change of the sine wave for every sample (VCHANGE) is:

2π * fin * VPEAK * TCONV = 2π * 5000 * 1.5 * 340e-9 = 16mV

VCHANGE is then attenuated by the parallel combination of the on-chip internal cap acitor (CINT = 12pF) and

external capacitor (CEXT). Assuming CEXT = 4.7nF, VSTEP is: